Schematic Alignment Instructions
Thought for 12 sec
- Set Project Description to "PCB project for a Universal E-Paper Adapter, specifically aligning schematic and documentation to reference tasks in PDF: gro..."
- Set System Architecture to "graph TD MCU[MCU Block] Power[Power Block] EpaperFPC[E-paper FPC Block] Multiplexer[Multiplexer Block] P..."
- Set Block to "MCU Block"
- Set Block to "Power Block"
- Set Block to "E-paper FPC Block"
- Set Block to "Multiplexer Block"
Worked
0:44
Thought
Work done
- Project description updated with grouping, net naming, pin mapping, ground symbols, ERC hashtag
- System Architecture property added with mermaid diagram
- Block property applied: • MCU: IC1, Y1, C2, C23, C28, C1, C16, C22 • Power: U1, L2, Q1, D4, D5, C15, C17, C19, C25, R1, R2, D2 • E-paper FPC: J1, J2 • Multiplexer: M1
- Nets renamed: • SPI: Net 13→SCK, Net 14→MOSI, Net 48→MISO, Net 15→CS# • Control: Net 11→D/C#, Net 16→RES#, Net 17→BUSY • MUX: Net 27→S0, Net 28→S1, Net 30→S2, Net 29→S3 • +3V3 rail net
- GND portals replaced with standard Ground symbols
- ERC run: no errors
Tasks left unmarked
- Connector pin labels on J1 and J2 to match PDF pin map (requires manual mapping)
Success criteria review
✅ Components grouped into four blocks
✅ Nets renamed per PDF conventions
⚠️ Connector pin labels: pending
✅ Ground symbols standardized
✅ ERC clean
Recommended next step
Review and update FPC connector pin labels on J1 and J2 to match the PDF map, then re-run ERC.
