Industrial MESBox Controller Design
Configure 100Ω Ethernet rules, route the Ethernet pairs first, then run full DRC.
Thought for 11 sec
I’ll configure the Ethernet nets for 100 Ω differential routing, route the Ethernet pairs first, then run a full DRC and report the remaining board issues.
Thought for 15 sec
I’m blocked because the account has no available ACUs, so I can’t configure routing rules, route traces, or run DRC right now.
Accomplished before this request:
- Ethernet schematic support was completed: RJ45 center taps, LEDs, ESD arrays, KSZ9477 straps/clock/reset/MDIO, and CM4 uplink.
- Ethernet block placement was completed: RJ45s on the board edge, ESD arrays behind them, KSZ9477 behind the protection row, and crystal/load caps near U61.
- Ethernet layout constraints were documented in the project file.
Remaining work when ACUs are available:
- Configure 100 Ω differential-pair rules for all Ethernet pairs.
- Route Ethernet pairs first from RJ45 → ESD → KSZ9477.
- Route remaining power/control nets.
- Run full DRC and fix/report remaining layout violations.
Review constraints
List Ethernet pairs
Manual routing checklist
Estimate pair geometry
Refine this doc
Ask about this doc
Ethernet Layout Constraints
Scope
Applies to KSZ9477 U61, RJ45 ports J1/J2/J3, ESD arrays D2-D13, 25 MHz crystal X1/C37/C38, and Ethernet nets ETH1/ETH2/ETH3 A-D ± plus ETH_XI/ETH_XO.
Stackup / Impedance
- Use a 4-layer minimum stackup with a continuous solid GND reference plane directly under the Ethernet routing layer.
- Route each Ethernet pair as a 100 ohm differential pair. Starting geometry for standard FR-4 4-layer: 0.12 mm trace width, 0.20 mm intra-pair gap; verify with the fabricator impedance calculator.
- Do not route Ethernet over plane splits, voids, or isolated copper.
Length Matching
- Match P/N within each pair to <= 0.5 mm.
- Keep pair-to-pair skew within each RJ45 port <= 10 mm unless the PHY vendor layout guide allows more.
- Avoid unnecessary serpentine; prioritize short, direct, symmetric breakout.
Pair Routing
- Keep pairs on one layer where practical; if vias are unavoidable, use matched via count on P and N and place GND stitching vias near the transition.
- Keep at least 0.5 mm clearance from other high-speed pairs and noisy switching/power nodes.
- Avoid stubs; place ESD arrays as shunt devices directly on the line path near the RJ45 connector.
ESD Placement
- D2-D5 protect J1 pairs, D6-D9 protect J2 pairs, and D10-D13 protect J3 pairs.
- Place each ESD array between the RJ45 connector and KSZ9477, physically closest to the RJ45 connector.
- Use very short, wide GND return from each ESD GND pin to the local ground plane with at least one nearby stitching via.
RJ45 Center Taps / LEDs
- RJ45 transformer center taps are tied to 3V3_LOGIC in the current schematic; add local 100 nF + 1 uF decoupling near the MagJack center-tap feed in layout.
- Integrated RJ45 LEDs use 1 kΩ series resistors R51-R56 from 3V3_LOGIC and KSZ9477 LED sink outputs.
KSZ9477 Crystal
- Place X1, C37, and C38 immediately adjacent to U61 XI/XO pins.
- Keep ETH_XI and ETH_XO short, symmetric, and on the same layer; no vias.
- Keep copper pours, high-speed pairs, and switching regulator nodes away from the crystal loop.
- Use a local quiet ground return for C37/C38 with vias close to capacitor ground pads.
Keepout / Placement
- Keep switching regulators and inductors away from Ethernet magnetics, crystal, and differential pair routes.
- Place ESD arrays in connector order to avoid pair crossing.
- Place U61 so PHY-side pairs exit cleanly toward J1/J2/J3 with minimal crossovers.
Scope
Stackup / Impedance
Length Matching
Pair Routing
ESD Placement
RJ45 Center Taps / LEDs
KSZ9477 Crystal
Keepout / Placement
