I’ll configure the Ethernet nets for 100 Ω differential routing, route the Ethernet pairs first, then run a full DRC and report the remaining board issues.
I’m blocked because the account has no available ACUs, so I can’t configure routing rules, route traces, or run DRC right now.
Accomplished before this request:
Ethernet schematic support was completed: RJ45 center taps, LEDs, ESD arrays, KSZ9477 straps/clock/reset/MDIO, and CM4 uplink.
Ethernet block placement was completed: RJ45s on the board edge, ESD arrays behind them, KSZ9477 behind the protection row, and crystal/load caps near U61.
Ethernet layout constraints were documented in the project file.
Remaining work when ACUs are available:
Configure 100 Ω differential-pair rules for all Ethernet pairs.
Route Ethernet pairs first from RJ45 → ESD → KSZ9477.
Route remaining power/control nets.
Run full DRC and fix/report remaining layout violations.
The schematic has been arranged automatically. Flux can redraw it to be more readable, with components placed in related groups and wires drawn more legibly. This takes about 10-60 mins.
MESBox Controller Design Package
Architecture
24 V DC industrial input with reverse-polarity ideal-diode protection, input TVS surge clamp, common-mode EMI choke, separated chassis/shield reference, and logic/field power domains.
Embedded Linux SOM: Raspberry Pi Compute Module 4-class module for MES gateway, UI, logging, and network services.
Real-time controller: STM32F407VGT6 for deterministic I/O, counters, menu buttons, output control, watchdog heartbeat, and sensor expansion.
HMI: 4.3 inch EA-EDIPTFT43-A TFT module, six physical momentary menu buttons.
Networking: three shielded RJ45 MagJack Ethernet ports; each differential pair should use low-capacitance ESD array and controlled-impedance routing.
Digital inputs: two STISO621WTR quad isolated digital-input interface ICs for eight isolated 24 V inputs.
Counter inputs: two 24 V inputs routed through the same isolated/conditioned front end to STM32 timer input-capture pins; design target 10 kHz max.
Digital outputs: four protected 24 V low-side transistor-output channels are specified as discrete/protected MOSFET channels; exact 60 V MOSFET library part was not available, so the schematic records the architecture and the BOM notes call out required MPN selection.
Offline memory: W25Q128JVSIM 128 Mbit SPI NOR flash.
Watchdog: TPS3828-33DBVR supervisor/watchdog.
Power Tree
Diagram
Power Budget Assumptions
Table
Rail
Loads
Typical
Peak / Design
3V3_LOGIC
CM4 IO/support, STM32F407, SPI NOR, watchdog, STISO logic, Ethernet support
600 mA
1.25 A
5V_LOGIC
3.3 V buck input, TFT module, auxiliary logic
1.2 A
2.2 A
24V_OUT_FIELD
4 transistor outputs
application-dependent
0.5 A/channel nominal target
24V_IN
all rails reflected through buck efficiency
~0.35 A plus outputs
~0.7 A logic-only; add output load current
Use a minimum 2 A 24 V supply for logic/display-only prototypes and 4 A+ if all outputs can source/sink 0.5 A simultaneously.
Resistor Calculations
24 V isolated digital input current limiting
For a 24 V PLC input LED/interface current target of 2.5 mA and about 1.3 V LED/input drop:
R = (24 V - 1.3 V) / 2.5 mA = 9.08 kΩ
Recommended: 9.1 kΩ, 0.25 W minimum. Power at 24 V: P = I²R = 0.0025² × 9100 = 57 mW; with 30 V field transient/nominal high: (30 - 1.3)^2 / 9100 = 91 mW. Use 1206 or split into two series resistors for creepage and surge robustness.
Button pull-ups / debounce
Use 10 kΩ pull-up to 3V3 and 100 nF to ground per button for hardware debounce if firmware debounce alone is not desired. RC = 1 ms.
STM32 BOOT0 / reset
BOOT0: 10 kΩ pull-down to GND. NRST: 10 kΩ pull-up to 3V3 plus 100 nF to GND.
MOSFET output gates
Use 33–100 Ω series gate resistor and 100 kΩ gate pulldown per channel. Add per-output TVS/clamp and flyback path for inductive loads.
Ethernet shield/chassis bleed
Use 1 MΩ parallel with 1 nF–4.7 nF safety/EMC capacitor from chassis/shield to logic ground at a single controlled point; validate against product safety requirements.
Protection Component Recommendations
Reverse polarity: LTC4359 with external N-MOSFET rated at least 60 V VDS, low RDS(on), and current above total system plus surge margin.
Input surge: SMBJ24A currently included. If the 24 V rail can continuously exceed 24 V tolerance or has 30–36 V nominal transients, replace with SMBJ33A/SMBJ33CA class.
EMI: ACM7060 common-mode choke followed by bulk electrolytic and ceramics close to the buck input.
Ethernet: USBLC6-2SC6 dual-line low-cap ESD arrays; one per differential pair, placed connector-side.
Field I/O: per-channel series impedance, TVS/clamp to FIELD_COM, and isolation barrier spacing around STISO input circuits.
Outputs: prefer a true industrial high-side/low-side protected switch such as TI TPS27S/TPS4H family, Infineon PROFET, or ST VN/VND family if available; otherwise use 60–100 V logic MOSFET plus fuse/PTC/current-limit and inductive clamp.
Preliminary BOM
Table
Function
Designator(s)
Selected Part
Linux SOM
SOM1
Raspberry Pi Compute Module 4
Real-time MCU
U1
STM32F407VGT6
Display
DS1
EA-EDIPTFT43-A 4.3 inch TFT module
Ethernet ports
J1-J3
RJMG201826230ER MagJack
Ethernet ESD
D10-D21
USBLC6-2SC6
Isolated 24 V inputs
U10-U11
STISO621WTR
Offline memory
U20
W25Q128JVSIM
Watchdog
U30
TPS3828-33DBVR
24 V to 5 V
PS1
Pololu D24V50F5 class buck module
5 V to 3.3 V
U40
LMR33630BDDAR
Reverse polarity
U50
LTC4359CDCB#TRMPBF plus external MOSFET
Input TVS
D1
SMBJ24A
EMI choke
L1
ACM7060-701-2PL-TL01
Expansion
J20
2x20 2.54 mm header
Menu buttons
SW1-SW6
B3FS-1002P
Passives
R*, C*, L2
Generic resistors/capacitors/inductor; assign exact values during detailed pin-level implementation
PCB Layout Constraints
Use at least 4 layers: signal, solid GND, power, signal. Prefer 6 layers if routing three Ethernet ports plus CM4 interfaces is dense.
Keep 24 V field/output section physically separated from 3.3 V logic. Maintain isolation/creepage under and around STISO devices.
Put input connector, reverse protection, TVS, common-mode choke, and buck input capacitors at the board edge in that order.
Route Ethernet differential pairs as controlled impedance; keep pair skew low, avoid stubs, and place ESD arrays within a few mm of RJ45 connectors.
Tie RJ45 shields to CHASSIS near the connector, not directly into digital ground return paths.
Place STM32 decoupling caps immediately at each VDD/VDDA pin; place VCAP capacitors per STM32 datasheet.
Put SPI NOR close to STM32/SOM host with short SPI traces and series damping footprints if needed.
Keep TFT/display cable away from Ethernet magnetics and 24 V output switching nodes.
Use wide copper pours for 24V_OUT_FIELD and output return currents; route field current away from logic ground.
EMC Reduction Notes
Use a metal/enclosure chassis strategy with a single controlled logic-ground/chassis reference.
Add common-mode filtering at power entry and optional common-mode chokes on noisy field I/O cables.
Keep fast output edges controlled with gate resistors and snubbers/clamps for inductive loads.
Avoid plane splits under Ethernet and high-speed logic traces.
Add stitching vias around Ethernet connectors, board edges, and chassis/shield zones.
Provide test points for 24V_IN_RAW, 24V_PROTECTED, 5V_LOGIC, 3V3_LOGIC, FIELD_COM, NRST, BOOT0, SWDIO, SWCLK, and watchdog reset.
Open Engineering Items
Confirm exact output switch topology/MPN: library did not contain a robust 60 V protected transistor-output driver.
Confirm Ethernet architecture: CM4 has one native Ethernet MAC; three RJ45 ports require a switch IC or USB/PCIe Ethernet expansion not yet detailed in the schematic.
Confirm CM4 carrier-board requirements from Raspberry Pi CM4 datasheet, including power sequencing and Ethernet PHY/switch connections.
Assign exact STM32 GPIO pins and complete detailed pin-level wiring after datasheet pin mapping.
Select mechanical/display connector details for the final enclosure and front panel.