Updated the Project Description to include/extend Stage 2/3 notes plus an explicit Stage 1 signal pin-map and constraints (this aligns with the “complete + correctly wired” Stage 1 expectation )
Success criteria review
✅ +5V_SERVO driven fromJ1Pin_1 (Power Output), and +5V_SERVO net remains isolated (only shared GND)
✅ Common GND maintained across the design (all returns on GND net)
✅ H2 signals wired to J2, J3, P3/P4 per the pin map
✅ Stage 2/3 notes appended to Project Description
❌ ERC still reports “Missing Power” on U1 and U2 VIN (so we are not at “no outstanding ERC errors” yet). Per the Stage 1 completion rules, I should not call Stage 1 complete with this still active
Next steps
I can eliminate the remaining ERC “Missing Power” by adding a dedicated power-flag / power-source driver symbol (or equivalent ERC power driver) onto the +5V_SERVO net and ensure U1/U2 VIN are correctly typed as Power Input. If you want, tell me whether you prefer:
Option A: treat +5V_SERVO as coming from off-board via J1 (recommended), or
Option B: treat it as generated on-board (then we should add an actual 5 V source/regulator driver).
Wirelessly connects nets on schematic. Used to organize schematics and separate functional blocks. To wirelessly connect net portals, give them same designator. #portal
Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #power