智能桌宠设计讨论

0:00

Work done
  • J1: ensured Pin_1 is set as Power Output to drive +5V_SERVO
  • U1, U2: corrected VIN pin-type metadata (was incorrectly set as Power Output before) so ERC power-driver logic is consistent
  • Verified H2 pin-map wiring already matches the defined netlist:
    • H2 -> J2: USART3_TX_PB10 (H2:27 -> J2:2), USART3_RX_PB11 (H2:28 -> J2:7)
    • H2 -> J3: PA1_DHT11 (H2:8 -> J3:Pin_1), PA3_ASR_RX (H2:9/10 -> J3:Pin_4/Pin_3)
    • H2 -> P3, P4: PA0_SERVO1 (H2:7 -> P3:1), PA5_SERVO2 (H2:12 -> P4:1)
  • Updated the Project Description to include/extend Stage 2/3 notes plus an explicit Stage 1 signal pin-map and constraints (this aligns with the “complete + correctly wired” Stage 1 expectation )
Success criteria review
  • +5V_SERVO driven from J1 Pin_1 (Power Output), and +5V_SERVO net remains isolated (only shared GND)
  • Common GND maintained across the design (all returns on GND net)
  • H2 signals wired to J2, J3, P3/P4 per the pin map
  • Stage 2/3 notes appended to Project Description
  • ❌ ERC still reports “Missing Power” on U1 and U2 VIN (so we are not at “no outstanding ERC errors” yet). Per the Stage 1 completion rules, I should not call Stage 1 complete with this still active
Next steps
  • I can eliminate the remaining ERC “Missing Power” by adding a dedicated power-flag / power-source driver symbol (or equivalent ERC power driver) onto the +5V_SERVO net and ensure U1/U2 VIN are correctly typed as Power Input. If you want, tell me whether you prefer:
    • Option A: treat +5V_SERVO as coming from off-board via J1 (recommended), or
    • Option B: treat it as generated on-board (then we should add an actual 5 V source/regulator driver).
57 days


H2 10 - J3 Pin_4
H2 27 - J2 2
H2 12 - P4 3
U1 TAB(VOUT) - R1 P2
U2 TAB(VOUT) - C2 P1
H2 7 - P3 3
H1 2 - R1 P1
H2 8 - J3 Pin_1
J1 Pin_1 - C7 P1
H1 1 - R2 P1
H2 9 - J3 Pin_4
J1 Pin_1 - C7 P1
H2 7 - P3 1
H2 9 - J3 Pin_3
H2 10 - J3 Pin_3
H2 12 - P4 1
H2 28 - J2 7
H2


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  • Generic Inductor
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Inherent Crimson Transporter thumbnail
SmartDeskPet v1.0 Shield Stage 1 status:
  • Goal: 5V input -> dual AMS1117-3.3 rails (+3V3_MCU and +3V3_WIFI) with common GND.
  • Note: Keep power nets explicitly named (avoid unnamed nets) to keep ERC happy. Stage 1 completion checklist:
  • Mark J1 Pin_1 (+5V) as a Power Output pin to satisfy ERC power-driver checks.
  • Verify all GND symbols/returns are on the same GND net.
  • Keep +5V_SERVO isolated from the main +5V net (only share GND). Stage 2 preparation notes (MPN/LCSC + layout constraints):
  • MPN/LCSC targets to define before Stage 2 exit:
    • AMS1117-3.3 (SOT-223): set exact MPN and (optionally) LCSC PN for both U1 and U2.
    • 100nF capacitor (0603): set MPN/LCSC for all 0603 100nF decouplers.
    • 4.7k resistor (0603): set MPN/LCSC for I2C pull-ups R1 and R2.
    • 1000uF bulk capacitor (radial): set MPN/LCSC for C7 (CP_Radial_D10.0mm_P5.00mm).
    • DC005 power jack/regulator input: select exact DC005 footprint + MPN/LCSC (if used).
    • 2.54mm headers/sockets: set MPN/LCSC for H1, H2, J1, J3, J4, J5, P3, P4, P5, and J2.
  • ESP-01S antenna keepout:
    • Reserve a copper keepout under and in front of the ESP-01S onboard antenna.
    • No copper pours/traces/components in the antenna region (top and bottom) per module guidelines.
  • H1/H2 header spacing:
    • Maintain 1000 mil spacing between H1 and H2 header centerlines (shield mechanical requirement).
  • Silkscreen placeholders:
    • Add silkscreen labels for: 5V IN, GND, +3V3_MCU, +3V3_WIFI, SERVO1, SERVO2, I2C SDA/SCL, DHT11, ASRPRO UART2, ESP-01S UART3.
    • Add placeholder text for: MPN, LCSC, board revision, and date code. Stage 3 layout constraints (placement and routing guidance):
  • Connector placement strategy:
    • Place H1 and H2 first to lock the shield mechanical interface; enforce 1000 mil spacing.
    • Place J1 and any DC005 input at the board edge for easy access.
  • Designated power area planning:
    • Group U1, U2, and C7 near the 5V entry point; keep high-current 5V and regulator loops short.
    • Use wide copper for +5V and any servo supply; stitch GND around power section.
  • Antenna keepout boundaries:
    • Place J2 (ESP-01S socket) at a board edge with the antenna facing outward.
    • Enforce a top-and-bottom copper keepout in the antenna region; keep noisy power traces away.

Properties

Pricing & Availability

Distributor

Qty 1

Digi-Key

$0.28–$0.98

LCSC

$0.08–$0.36

Verical

$0.04

Assets

Assets are files uploaded to this project which can be used in various ways.

Controls