Power Section Design Update
Thought for 6 sec
To duplicate the project in Flux:
- Open the current project.
- Click the project/menu controls near the project name.
- Choose Fork or Duplicate.
- Create the first copy and name it: GLECS HV Board.
- Go back to the original project and duplicate/fork again.
- Name the second copy: GLECS Logic Board.
Keep the original untouched as your master reference.
After both copies exist, the split workflow is:
- In GLECS HV Board, keep HV parts + J_LINK and remove/exclude logic parts.
- In GLECS Logic Board, keep logic parts + matching J_LINK and remove/exclude HV parts.
- Verify J_LINK pinout matches exactly in both projects.
Duplicate this project twice, keeping the original intact.
Name the first copy "GLECS HV Board" and the second copy
"GLECS Logic Board". Confirm when both copies exist.
Worked for 1 min 58 sec
Cloned a project
GLECS HV Board
Power-section schematic for a 12V DC input generating +4V for a 4G module, +5V, and +3V3 rails with input TVS protection and regulator thermal notes.
Cloned a project
GLECS Logic Board
Power-section schematic for a 12V DC input generating +4V for a 4G module, +5V, and +3V3 rails with input TVS protection and regulator thermal notes.
Both copies now exist, and the original project was left intact.
- GLECS HV Board: /ddsdasxdas/glecs-hv-board
- GLECS Logic Board: /ddsdasxdas/glecs-logic-board
Split both boards
Prepare HV board
Prepare logic board
Create split table
Verify J_LINK contract
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Power Section Notes
Scope
Build only the power section from the user-provided requirements:
- 12V DC input through a 2-pin screw terminal.
- P6SMB33CA TVS from +12V to GND.
- 220uF input bulk capacitor.
- LMR33630ADDAR buck converter generating +4V for a 4G module.
- Existing 100uF tantalum plus added 470uF low-ESR electrolytic bulk capacitance on +4V for A7672SA transmit bursts.
- AMS1117-5.0 linear regulator generating +5V from +12V.
- AMS1117-3.3 linear regulator generating +3V3 from +5V.
- Single GND return net.
Datasheet-backed implementation notes
- LMR33630ADDAR DDA pinout: PGND, VIN, EN, PG, FB, VCC, BOOT, SW, exposed pad AGND.
- LMR33630 EN must not float; for always-on operation it is tied to VIN.
- LMR33630 PG is open-drain and may be left unconnected if unused.
- LMR33630 VCC requires a 1uF capacitor to GND and must not power external loads.
- LMR33630 BOOT uses 100nF from BOOT to SW.
- LMR33630 adjustable FB reference is nominally 1.000V. For +4.0V: Rtop/Rbottom = 3. Implemented as 100k from +4V to FB and 33.2k from FB to GND.
- AMS1117 fixed regulators use SOT-223 pinout: pin 1 GND/ADJ, pin 2 VOUT, pin 3 VIN, tab VOUT. Output tantalum capacitance >=22uF is required for stability; user requested 220uF.
Load currents and thermal validation
User-provided load currents:
- +3V3 rail: 60mA typical, 100mA maximum.
- +5V rail direct loads: 30mA typical, 50mA maximum.
- +4V rail: 200mA average, 2A peak A7672SA transmit bursts.
Thermal calculations:
- U_3V3 dissipates (5V - 3.3V) * I_3V3 = 1.7V * 0.10A = 0.17W maximum.
- Because +3V3 is derived from +5V, U_5V supplies both direct +5V load current and U_3V3 input current. Worst-case U_5V current is about 50mA + 100mA = 150mA, so U_5V dissipates (12V - 5V) * 0.15A = 1.05W maximum. Typical U_5V dissipation is about 7V * (30mA + 60mA) = 0.63W.
- U_5V therefore still needs careful copper heat spreading and temperature verification under maximum load; it is not validated by considering only the direct +5V load.
- The requested 10x10mm copper pads and thermal vias should be implemented during PCB layout, but note that AMS1117 SOT-223 tab is VOUT, not GND. Any thermal vias directly tied to the tab pad must connect to the corresponding output rail, not GND.
Open validation assumptions
- +4V buck load is 200mA average and 2A peak burst, within the LMR33630 3A rating if layout, inductor current rating, and local module decoupling are adequate.
- P6SMB33CA is a bidirectional TVS with 28.2V standoff and about 45.7V clamp at pulse current; it protects against large surges but does not protect AMS1117 devices from sustained moderate overvoltage above their 15V abs max.
Scope
Datasheet-backed implementation notes
Load currents and thermal validation
Open validation assumptions
