Power Section Design Update

uyfersdu6y

Placement is locked — do not move components. Make these two fixes: FIX 1 — Via layer span (clears all 52 "Invalid Layer" errors): All 52 Smart Vias were created with a Through-hole L1→L4 span, but this board is 2-layer. Redefine the via span for these vias to Top Copper → Bottom Copper (the only two copper layers). Apply to all 52 invalid vias. Do not move or delete the vias — only correct their layer span. FIX 2 — Clear the pad overrides on C_5V (clears the 2 Component Override warnings): Remove the pad-level keepout/minKeepout overrides on C_5V pads P1 (+5V) and P2 (GND) so the pads use the normal board design rules. Do not move C_5V. Then re-run DRC and report the remaining error count by type.

flux

Completed:
  • Fixed all 52 Invalid Layer via errors by changing the Smart Vias from invalid L1→L4 span to valid Top→Bottom for the 2-layer board.
  • Removed inline C_5V pad keepOut, minKeepOut, and active rules without moving C_5V or any components.
Latest DRC counts:
  • Invalid Layer: 0
  • Overlapping copper: 0
  • Airwires: 34
  • Floating copper: 20
  • Component Override warnings: 2 still remain on C_5V P1/P2
  • Other checked categories: no open protected-intrusion, under-connected-via, pad-access, outside-board, or component-body-overlap items reported.
Remaining:
  • The two C_5V override warnings are separate override-ruleset objects (active=false !important) that the current edit tool did not allow me to delete directly.
  • ACUs are now unavailable, so I can’t continue further in this turn.
Show override selectors
List airwire nets
Group floating copper
Rerun after cleanup
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  • Generic Resistor
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GLECS Logic Board thumbnail
Power-section schematic for a 12V DC input generating +4V for a 4G module, +5V, and +3V3 rails with input TVS protection and regulator thermal notes.

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