Project Start

flux

The first schematic pass is complete, but my independent connectivity check found several local support nets stranded as one-pin nets (gate drive, timer/PWR/OVLO, buck SW/BOOT/FB/EN, and the enable transistor base). I’m correcting those before presenting the schematic checkpoint.
Thought for 58 sec
Thought for 14 sec
Thought for 8 sec
Awaiting 1 background task
"Server PDB Schematic" completed.

flux

Built the first schematic pass for Server PDB Rev A:
  • Renamed and described the project.
  • Added 43 components covering the LM5069 hot-swap stage, three MOSFETs, TPS56637 buck, enable circuit, verified output connectors, test points, and support passives.
  • Created the Project Specification, Power Budget, and Board Bring-Up Plan.
  • Left J1 PwrBlade and J3 PICPWR unplaced because their exact variants and footprints remain unknown.
Important: the schematic is not yet safe to fabricate. Although ERC reported clean, my independent net inspection found stranded local connections around the LM5069, MOSFET gates, enable transistor, and buck converter—including GATE, TIMER, PWR, UVLO/OVLO, SW, BOOT, FB, and EN support networks. I dispatched a correction pass, but it could not be retrieved and independently verified before execution stopped.
Remaining work:
  • Confirm and repair every stranded support net.
  • Verify the requested 0.7 mΩ shunt and 2.2 µH inductor variants; the current library selections show different suffixes.
  • Obtain official J1/J3 drawings and verify J4/J5/J6 cable orientation.
  • Re-run connectivity/ERC review before advancing to PCB placement.
  • Complete high-current SOA, inrush, thermal, copper, and connector-rating analysis.
Execution stopped because your ACUs ran out.
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Project Specification
Status: Draft / schematic checkpoint
Project Overview
Prototype replacement server power distribution board, Rev A. The board distributes a nominal 12 V PSU input through a Kelvin shunt and LM5069-controlled three-MOSFET hot-swap stage, then feeds server power connectors and a 12 V-to-3.3 V buck. Rev A implements power distribution and active-low power enable only; it has no BMC or SMBus telemetry.
Intended Use
  • Prototype engineering and bench validation, not production-qualified.
  • Replacement server PDB in a nominal 180 mm × 56 mm mechanical envelope.
  • Final mating connector geometry, cable orientation, high-current construction, and thermals require validation before fabrication.
What the Device Should Do
  • Accept nominal 12 V at a raw-input interface as RAW_12V.
  • Measure input current across a 0.7 mΩ four-terminal Kelvin shunt, producing SENSE_12V after the shunt.
  • Use an LM5069 hot-swap controller and three parallel N-MOSFETs to create protected SW_12V.
  • Keep SW_12V and 3V3 off when PDB_ENABLE_L is open/high; turn them on when the motherboard pulls PDB_ENABLE_L low.
  • Distribute only SW_12V—never RAW_12V—to downstream connectors.
  • Generate 3V3 from SW_12V, then feed isolated branches 3V3_A and 3V3_B through independently removable 0 Ω 2512 links.
  • Provide accessible test points for RAW, switched 12 V, enable, and 3.3 V.
Main Features
  • LM5069MM-2/NOPB hot-swap control.
  • WSLP2726L7000FEA 0.7 mΩ, 1%, 7 W Kelvin shunt.
  • Three PSMN2R2-100SSE N-MOSFETs with individual 22 Ω gate resistors.
  • TPS56637RPAR 6 A synchronous buck and 2.2 µH IHLP3232 inductor.
  • Active-low motherboard enable using MMBT3904LT1G.
  • Motherboard, Micro-Fit, Mini-Fit Jr., and provisional/blocked high-current interfaces.
Mechanical System Architecture
  • PCB envelope: 180 mm × 56 mm, provisional until exact chassis mounting, connector datums, and drill patterns are confirmed.
  • Vertical THT connectors where specified.
  • No PCB layout is in scope at this checkpoint.
Text
PSU / chassis connector → 180 × 56 mm PDB → motherboard and peripheral harnesses
Electrical System Architecture
Text
PSU placeholder
  │ RAW_12V
  ▼
0.7 mΩ Kelvin shunt
  │ SENSE_12V
  ▼
3× parallel N-MOSF + LM5069 hot-swap
  │ SW_12V
  ├────────────→ J2/J4/J5/J6 downstream 12 V loads
  └→ TPS56637 buck → 3V3 → 0 Ω link → 3V3_A
                            └→ 0 Ω link → 3V3_B
Unified return: GND
Hardware Subsystems
IO J1 PSU Input
  • Exact Amphenol PwrBlade ULTRA MPN and drill pattern are TBD.
  • Do not claim mating geometry or create a guessed footprint.
  • Use only a real generic high-current interface if the library provides one without claimed mating geometry; otherwise omit J1 and document the fabrication blocker.
PROTECT U1 Hot Swap
  • U1: LM5069MM-2/NOPB, VSSOP-10/DGS.
  • RS1: WSLP2726L7000FEA, four-terminal Kelvin shunt.
  • Q1–Q3: PSMN2R2-100SSE in parallel from SENSE_12V to SW_12V.
  • Individual 22 Ω gate resistors.
  • UVLO divider: 30.1 kΩ / 10.0 kΩ, 1%, provisional ≈10 V threshold.
  • OVLO divider: 56.2 kΩ / 10.0 kΩ, 1%, provisional ≈16.5 V threshold.
  • RPWR: 15.8 kΩ. CTIMER: 150 nF X7R.
  • Local VIN bypass: 100 nF, 25 V, X7R.
  • PGD optional and intentionally unused if permitted by the datasheet/symbol.
  • Nominal current-limit estimate: 55 mV / 0.7 mΩ = 78.6 A.
  • Provisional continuous target: 60 A; shunt drop 42 mV, shunt dissipation 2.52 W at 60 A.
Active-Low Enable
  • PDB_ENABLE_L is J2 pin 14.
  • 47 kΩ from RAW_12V to enable node and 47 kΩ from node to GND establish ≈6 V when open.
  • Node drives QEN1 base through 330 kΩ; 1 MΩ base-emitter resistor; emitter to GND.
  • QEN1 collector pulls U1 UVLO low while the enable node is high/open.
  • Motherboard pull-low turns QEN1 off, allowing the UVLO divider to enable the hot-swap.
POWER U2 3V3 Buck
  • U2: TPS56637RPAR, provisional 6 A capability.
  • Input: local 100 nF plus 2× 22 µF, 25 V, X7R, 1210 (requested GRM32ER71E226KE15L).
  • L1: IHLP3232DZER2R2M01, 2.2 µH.
  • Bootstrap: 100 nF X7R from BOOT to SW, not GND.
  • Feedback: 45.3 kΩ top / 10.0 kΩ bottom, target ≈3.32 V for 0.6 V reference.
  • Enable divider: 100 kΩ from SW_12V to EN; 22 kΩ EN to GND.
  • Output: 3× 22 µF, 10 V, X7R, 1210 (requested GRM32ER71A226KE20L).
  • MODE and PG follow the verified datasheet recommendation; NC is explicitly no-connect.
  • Actual 3.3 V system load is unknown.
Separate 3.3 V Branches
  • 3V3 → RLA → 3V3_A and 3V3 → RLB → 3V3_B.
  • RLA and RLB are 0 Ω, 2512, independently removable.
  • 3V3_A and 3V3_B must not connect anywhere else.
IO J2 Motherboard
  • JST B24B-PHDSS-B, 24 positions, 2×12, 2.00 mm pitch, vertical THT.
  • Pin 14: PDB_ENABLE_L.
  • Pins 17, 19, 20, 21, 22, 23, 24: SW_12V.
  • Pin 18: GND.
  • Pins 1–13 and 15–16: intentionally unconnected in Rev A.
IO J3 PICPWR
  • Amphenol 10167520 PICPWR family; exact suffix TBD.
  • Measured power-row intent: bottom row +12 V, top row GND; sidebands S1–S12 unimplemented.
  • Omit the physical connector until exact suffix, pin numbering, mating drawing, and footprint are verified.
IO J4 4-Pin Power
  • Molex 43045-0427, Micro-Fit 3.0 2×2 vertical THT.
  • Exactly two contacts SW_12V and two contacts GND; actual terminal mapping must follow the verified manufacturer drawing.
IO J5 Riser Power
  • Molex 43045-0627, Micro-Fit 3.0 2×3 vertical THT.
  • Nonstandard mapping, based on viewed orientation:
    • Top row A=3V3_A, B=3V3_B, C=GND.
    • Bottom row D=SW_12V, E=GND, F=SW_12V.
  • Actual terminal numbers and viewed-side orientation must be recorded from the verified drawing. Do not treat as standard PCIe 6-pin.
IO J6 PCIe Power
  • Molex 0039281083 / 39-28-1083, Mini-Fit Jr. 2×4 vertical THT.
  • Standard power cavities connect to SW_12V; standard returns connect to GND.
  • Chassis-cable orientation/mirroring remains a fabrication blocker even after logical terminal numbers are resolved.
Interfaces and Connections

Table

NetPurpose
RAW_12VPSU-side 12 V before shunt
SENSE_12VPost-shunt / MOSFET source-side rail
SW_12VHot-swap controlled downstream 12 V
3V3Buck output before branch links
3V3_ARemovable branch A
3V3_BRemovable branch B
PDB_ENABLE_LMotherboard active-low power enable
GNDUnified return
Power and Runtime Expectations
  • Nominal input is approximately 12 V; final PSU tolerance/transients are not yet confirmed.
  • Provisional continuous SW_12V target is 60 A.
  • 3.3 V load is unknown; regulator capability is 6 A provisional, not a claimed system load.
  • No battery or runtime requirement.
Power Tree and Power Budget
See the separate Power Budget project file. Avoid double-counting the buck input current if the 60 A system target already includes all downstream loads.
Manufacturing and Assembly Expectations
  • Prototype only.
  • SMD passives by default: 0603/0805 as appropriate; 1210 for specified 22 µF capacitors; 2512 for removable 0 Ω links.
  • Exact manufacturer parts are required where specified.
  • Real library parts or datasheet-backed creation only; no invented geometry.
  • Four accessible test points are required.
Firmware-Relevant Hardware Requirements
None. Rev A has no MCU, BMC, SMBus, or telemetry.
Physical Design Expectations
  • Board envelope: 180 mm × 56 mm.
  • High-current copper, layer count/stackup, connector edge locations, mounting holes, component height, and chassis clearances are unresolved.
  • Layout must not begin until schematic review is accepted and fabrication-blocking interfaces are resolved.
Validation Criteria
Disabled / open enable
  • RAW_12V ≈12 V.
  • PDB_ENABLE_L ≈6 V.
  • SW_12V = 0 V.
  • 3V3 = 0 V.
Enabled / enable pulled low
  • RAW_12V ≈12 V.
  • PDB_ENABLE_L near 0 V.
  • SW_12V ≈12 V.
  • 3V3 ≈3.3 V.
Schematic checkpoint
  • All intended rails coherent and connector pins wired or marked no-connect.
  • No downstream connector receives RAW_12V.
  • 3V3 derives only from SW_12V.
  • 3V3_A and 3V3_B remain isolated except through RLA/RLB.
  • ERC and schematic-legibility checks run; real errors fixed and justified exceptions documented.
Important Design Decisions
  • Active-low enable uses a fail-disabled open-state bias and NPN UVLO clamp.
  • Three MOSFETs are paralleled with individual gate resistors.
  • Kelvin sense is kept distinct from the shunt's high-current path.
  • J1 and J3 physical connectors are omitted unless exact geometry is verified.
Assumptions
  • 12 V nominal source.
  • User-provided divider values and expected thresholds are provisional pending bench validation.
  • Unified ground is acceptable for Rev A.
  • 90% buck efficiency is used only for provisional worst-case budget reflection.
Explicit Unresolved / Fabrication-Blocking Items
  • J1 exact Amphenol PwrBlade ULTRA MPN, mating interface, drill pattern, and contact current rating.
  • J3 exact Amphenol 10167520 suffix, pinout, mating drawing, and footprint.
  • J4/J5/J6 viewed-side orientation and chassis cable mirroring confirmation.
  • Connector contact current ratings and current sharing.
  • Real server load profile and whether 60 A includes the buck input contribution.
  • Inrush target and downstream capacitance.
  • LM5069 TIMER/PWR validation for the actual inrush and fault profile.
  • MOSFET sharing, linear-mode SOA, transient stress, cooling, and thermal coupling.
  • Shunt and copper temperature rise.
  • PCB copper weight, layer count, final stackup, busbar strategy, clearances, mounting, and airflow.
  • Prototype bench validation before any production claim.
Change Notes
  • Rev A initial requirements captured.
  • Telemetry intentionally excluded.
  • Schematic-only task; PCB layout deferred.
  • Schematic implementation completed with J1 and J3 intentionally omitted because exact mating geometry is unresolved.
Schematic Implementation Record
  • LM5069 pin functions were checked against the TI pin table: SENSE=1, VIN=2, UVLO=3, OVLO=4, GND=5, TIMER=6, PWR=7, PGD=8, OUT=9, GATE=10.
  • The LM5069 pass MOSFET topology is drain at SENSE_12V and source/output at SW_12V; the shunt is between RAW_12V and SENSE_12V.
  • TPS56637 pin functions and the required BOOT-to-SW 0.1 µF connection were checked against the TI pin table.
  • TPS56637 MODE is tied to GND for Eco-mode; PG is intentionally unused, and NC is explicitly no-connect. The datasheet permits MODE-to-GND for Eco-mode and requires NC to float.
  • J4 logical assignment: pins 1–2=SW_12V, pins 3–4=GND. Final viewed-side orientation remains a fabrication check.
  • J5 logical assignment: pin 1=3V3_A, pin 2=3V3_B, pin 3=GND, pin 4=SW_12V, pin 5=GND, pin 6=SW_12V. This is intentionally nonstandard and follows the requested row mapping; chassis-side orientation remains a fabrication check.
  • J6 logical assignment: pins 1–3=SW_12V, pins 4–8=GND. Final cavity mirroring against the chassis cable remains blocked.
  • J1: no physical part added. No acceptable library placeholder without claimed mating geometry was found.
  • J3: no physical part added. Exact PICPWR suffix, pinout, and footprint remain unresolved.
  • Exact-value WSLP2726 and IHLP3232DZ instances use verified same-family library geometry with instance MPN/electrical properties updated to the requested variants; final footprint audit remains required before layout.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • Mechanical System Architecture

  • Electrical System Architecture

  • Hardware Subsystems

  • IO J1 PSU Input

  • PROTECT U1 Hot Swap

  • Active-Low Enable

  • POWER U2 3V3 Buck

  • Separate 3.3 V Branches

  • IO J2 Motherboard

  • IO J3 PICPWR

  • IO J4 4-Pin Power

  • IO J5 Riser Power

  • IO J6 PCIe Power

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Validation Criteria

  • Disabled / open enable

  • Enabled / enable pulled low

  • Schematic checkpoint

  • Important Design Decisions

  • Assumptions

  • Explicit Unresolved / Fabrication-Blocking Items

  • Change Notes

  • Schematic Implementation Record