Project Start

flux

The first schematic pass is complete, but my independent connectivity check found several local support nets stranded as one-pin nets (gate drive, timer/PWR/OVLO, buck SW/BOOT/FB/EN, and the enable transistor base). I’m correcting those before presenting the schematic checkpoint.
Thought for 58 sec
Thought for 14 sec
Thought for 8 sec
Awaiting 1 background task
"Server PDB Schematic" completed.

flux

Built the first schematic pass for Server PDB Rev A:
  • Renamed and described the project.
  • Added 43 components covering the LM5069 hot-swap stage, three MOSFETs, TPS56637 buck, enable circuit, verified output connectors, test points, and support passives.
  • Created the Project Specification, Power Budget, and Board Bring-Up Plan.
  • Left J1 PwrBlade and J3 PICPWR unplaced because their exact variants and footprints remain unknown.
Important: the schematic is not yet safe to fabricate. Although ERC reported clean, my independent net inspection found stranded local connections around the LM5069, MOSFET gates, enable transistor, and buck converter—including GATE, TIMER, PWR, UVLO/OVLO, SW, BOOT, FB, and EN support networks. I dispatched a correction pass, but it could not be retrieved and independently verified before execution stopped.
Remaining work:
  • Confirm and repair every stranded support net.
  • Verify the requested 0.7 mΩ shunt and 2.2 µH inductor variants; the current library selections show different suffixes.
  • Obtain official J1/J3 drawings and verify J4/J5/J6 cable orientation.
  • Re-run connectivity/ERC review before advancing to PCB placement.
  • Complete high-current SOA, inrush, thermal, copper, and connector-rating analysis.
Execution stopped because your ACUs ran out.
Sign up to send

Files

Schematic

Layout

3D View

Board Bring-Up Plan
Safety Preconditions
  • Treat this as a high-current prototype. Use a current-limited bench source, fused leads, eye protection, and a nonconductive work surface.
  • Do not connect a motherboard or peripheral harness until every preceding step passes.
  • Confirm J1/J3 fabrication blockers and all connector orientation/mirroring before assembling a board.
  • Start with a low current limit and no downstream load.
Required Equipment
  • Current-limited 12 V bench supply.
  • DMM with continuity, resistance, and DC voltage modes.
  • Oscilloscope and suitable probes for startup/inrush work after basic checks pass.
  • Safe temporary method to pull PDB_ENABLE_L to GND.
1. Unpowered Continuity and Short Checks
  1. Visually inspect polarity, orientation, solder bridges, shunt Kelvin terminals, MOSFET orientation, and connector loading.
  2. Verify continuity of the intended power path: input interface → RAW_12V → shunt → SENSE_12V → MOSFET bank → SW_12V.
  3. Verify no direct short between RAW_12V, SENSE_12V, SW_12V, 3V3, 3V3_A, 3V3_B, and GND.
  4. Verify 3V3_A connects to 3V3 only through RLA and 3V3_B only through RLB.
  5. Verify no downstream 12 V connector pin connects directly to RAW_12V; all must connect to SW_12V.
  6. Verify J2 pins 1–13 and 15–16 are open; pin 14 is PDB_ENABLE_L; pin 18 is GND; pins 17 and 19–24 are SW_12V.
  7. Verify the installed J4/J5/J6 cavity orientation against the approved harness drawing before applying power.
Pass: no unintended low-resistance shorts and every rail/connector continuity path matches the schematic.
2. Energize and Verify RAW
  1. Leave PDB_ENABLE_L open and leave all loads disconnected.
  2. Set the bench supply to approximately 12 V with a conservative current limit.
  3. Energize the board.
  4. Measure at TP_RAW.
Pass: RAW_12V is approximately 12 V and supply current is low/stable.
3. Verify Open-State Enable
  1. With enable still open, measure TP_EN.
  2. Measure TP_SW12 and TP_3V3.
Expected: PDB_ENABLE_L approximately 6 V, SW_12V 0 V, and 3V3 0 V.
Fail action: power down immediately if switched rails rise unexpectedly; inspect QEN1 orientation, the 47 kΩ bias divider, UVLO network, and MOSFET orientation.
4. Safely Pull Enable Low
  1. Use a controlled jumper or switch to connect PDB_ENABLE_L to GND.
  2. Do not probe or attach downstream hardware while changing the enable state.
  3. Observe bench-supply current and stop if it reaches the current limit unexpectedly.
Pass: TP_EN is near 0 V without abnormal source current.
5. Verify SW_12V
  1. Measure TP_SW12 after enable is pulled low.
  2. Check for a controlled rise toward the input voltage.
  3. If using an oscilloscope, observe the inrush ramp and verify no oscillation or repeated fault/retry cycling.
Expected: SW_12V approximately 12 V.
Fail action: power down and inspect LM5069 UVLO/OVLO/TIMER/PWR networks, shunt Kelvin routing, gate resistors, MOSFET pinout, and downstream capacitance.
6. Verify 3V3
  1. Measure TP_3V3 only after SW_12V is stable.
  2. Confirm the buck starts cleanly and the output is regulated.
  3. Check 3V3_A and 3V3_B through their installed links.
Expected: 3V3 approximately 3.3 V; branches match 3V3 when their respective links are fitted.
Fail action: power down and inspect U2 VIN/PGND/AGND, BOOT-to-SW capacitor, inductor, feedback divider, enable divider, MODE connection, and input/output capacitors.
7. Load Progression
  1. Apply small dummy loads first to SW_12V and then 3V3.
  2. Increase load gradually while monitoring rail voltage, current, shunt temperature, MOSFET temperatures, inductor temperature, connector temperature, and copper temperature rise.
  3. Characterize startup with the actual downstream capacitance before connecting server hardware.
  4. Do not approach the 60 A provisional target until connector ratings, copper/stackup, SOA, inrush, and cooling have been validated.
8. Connect Motherboard and Peripherals Last
Only after all prior checks pass:
  1. Power down.
  2. Connect the motherboard harness and confirm J2 orientation.
  3. Re-energize with enable open; confirm the disabled-state voltages again.
  4. Exercise motherboard pull-low enable and verify SW_12V then 3V3 in sequence.
  5. Power down before adding each peripheral/riser/PCIe harness, repeating continuity and orientation checks each time.
Acceptance Record
Record bench-supply settings, open-state voltages, enabled-state voltages, startup waveforms, load current, component temperatures, connector temperatures, and any LM5069 retries or fault events. The board is not approved for server installation until the unresolved fabrication and high-current validation items in the Project Specification and Power Budget are closed.

  • Safety Preconditions

  • Required Equipment

  • 1. Unpowered Continuity and Short Checks

  • 2. Energize and Verify RAW

  • 3. Verify Open-State Enable

  • 4. Safely Pull Enable Low

  • 5. Verify SW_12V

  • 6. Verify 3V3

  • 7. Load Progression

  • 8. Connect Motherboard and Peripherals Last

  • Acceptance Record