Motor Controller for a Robot Arm
Worked for 4 mins 36 sec
Created 2 project docs
Board Bring-Up Plan — Closed-Loop DC Motor Controller
Equipment: current-limited bench supply, DMM, oscilloscope, ST-LINK/SWD debugger, USB-UART adapter, encoder simulator or known encoder, dumm...
Implemented and verified the schematic for the closed-loop brushed DC motor controller.
What was completed:
- Added a robust 12 V nominal motor-controller architecture: MC33926 H-bridge, STM32G431 MCU, INA240 current sense, LMR33630 3.3 V buck, LM74700 reverse protection, encoder conditioning, connectors, LEDs, and protection.
- Wired power, motor drive, current sensing, encoder A/B/Z, SWD, UART control, reset/BOOT0, and fault/status paths.
- Ran schematic/ERC checks; there are no open ERROR/WARNING/UNCERTAIN checks in the reviewed schematic categories.
Project files created/updated:
Open items:
- Layout is not started yet; high-current motor paths, shunt Kelvin routing, buck layout, and thermal copper will be critical.
- Firmware starter is a HAL bring-up baseline; final PID/current-limit tuning still needs motor characterization.
Suggested next steps:
- Set PCB constraints: board size, stackup, current-aware trace widths, and clearance rules.
- Place components with power path and thermal priorities.
- Route the PCB, then run DRC/PI checks.
- Add test points for 3V3, VM_PROT, HBRIDGE_EN, current sense, and encoder signals.
Set constraints and layout
Set PCB constraints
Place components
Route the PCB
Add test points
Review BOM risks
Refine this doc
Ask about this doc
Design Notes
Datasheet-Backed Component Choices
H-Bridge: NXP MC33926PNB
- Motor supply: VPWR class 5 V to 28 V; selected for 12 V nominal robotics motor supply.
- Supports bidirectional brushed DC motor control with IN1/IN2, D1/D2 disable, EN, INV, and SLEW inputs.
- Datasheet notes PWM up to 20 kHz; slow slew mode limits PWM below 11 kHz.
- Integrated protection: current limiting, short-circuit latch-off, overtemperature latch-off, undervoltage behavior, status flag.
- Required external support used in schematic plan:
- VPWR low-ESR bulk capacitance, 100 uF class, plus local 100 nF bypass.
- Charge-pump reservoir capacitor from CCP to VPWR, allowed 30 nF to 100 nF; 33 nF selected.
- SF active-low open-drain fault pull-up to 3.3 V.
- FB current mirror output support: 270 ohm to GND plus optional 1 uF filter if disable-PWM strategy is used.
MCU: STM32G431CBT6
- 3.3 V operation within datasheet VDD range 1.71 V to 3.6 V.
- Control-oriented Cortex-M4F with encoder-capable timers, PWM timers, ADC, USART/UART, FDCAN-capable pins, and SWD/JTAG.
- Power decoupling per datasheet:
- Each VDD/VSS pair gets 100 nF.
- VDD rail gets 4.7 uF bulk.
- VDDA/VSSA gets 10 nF + 1 uF filtering/decoupling.
- VREF+ gets 100 nF + 1 uF when used for ADC reference.
- BOOT0 on PB8 should be controlled; use pull-down for normal boot.
- NRST has embedded weak pull-up; add reset button and small reset capacitor for robust manual reset.
Current Sense: INA240A1D + 10 mOhm Shunt
- INA240 selected because datasheet explicitly targets PWM motor current sensing and supports -4 V to 80 V common-mode independent of supply.
- Gain: 20 V/V.
- Shunt: 10 mOhm inline with motor lead.
- Output bias: REF1 to 3.3 V and REF2 to GND gives 1.65 V zero-current midpoint.
- Current span:
- 2 A => 20 mV shunt => 0.4 V output swing, so output is about 1.25 V to 2.05 V.
- 5 A transient => 50 mV shunt => 1.0 V output swing, so output remains about 0.65 V to 2.65 V.
- INA240 supply decoupling: 100 nF close to VS/GND.
- Layout requirement: Kelvin route shunt sense traces.
Encoder Conditioning: SN74LVC3G17DCUR
- Triple non-inverting Schmitt buffer.
- VCC range 1.65 V to 5.5 V; powered from 3.3 V.
- Inputs accept up to 5.5 V at any valid VCC, useful for robotics encoders.
- 100 nF bypass cap required at VCC.
- All unused inputs must be tied to VCC or GND; all three channels are used for A, B, and Z.
3.3 V Buck: LMR33630BDDAR
- Selected instead of LDO for thermal efficiency from 12 V input.
- HSOIC/DDA package selected after ERC review to avoid the VQFN package's NC-to-SW pad conflict; datasheet pinout is PGND, VIN, EN, PG, FB, VCC, BOOT, SW, with thermal pad to GND.
- Datasheet 400 kHz 3.3 V component set used:
- L = 6.8 uH.
- RFBT = 100 kΩ, RFBB = 43.2 kΩ.
- CIN = 10 uF + 220 nF minimum; split/local ceramic capacitance recommended.
- COUT = 4 x 22 uF rated capacitance.
- CBOOT = 100 nF from BOOT to SW.
- CVCC = 1 uF from VCC to GND.
- EN tied to protected VM when always-on.
Reverse/Input Protection: LM74700-Q1 + DMT6008LFG + SMBJ33CA
- LM74700 ideal diode controller with external N-channel MOSFET for reverse polarity and reverse-current blocking.
- Datasheet recommends 60 V MOSFET, VGS max >= 15 V, and RDS(on) near 6.7 mΩ to 16.7 mΩ for a 3 A nominal design; DMT6008LFG 60 V, low-RDS(on) PowerDI MOSFET matches this class.
- VCAP: minimum 0.1 uF; selected 100 nF.
- Input capacitance: minimum 22 nF at ANODE; output capacitance minimum 100 nF, 47 uF typical holdup selected.
- SMBJ33CA bidirectional TVS selected for 12 V input transient protection.
Open Layout Checks
- Confirm MC33926 thermal pad copper area supports 2 A continuous in the selected enclosure/ambient.
- Size motor supply traces/pours for at least 2 A continuous and transient current.
- Place input TVS and ideal diode stage directly at the input connector.
- Place shunt in motor-current path and keep INA240 Kelvin traces short, symmetric, and away from switching nodes.
Datasheet-Backed Component Choices
H-Bridge: NXP MC33926PNB
MCU: STM32G431CBT6
Current Sense: INA240A1D + 10 mOhm Shunt
Encoder Conditioning: SN74LVC3G17DCUR
3.3 V Buck: LMR33630BDDAR
Reverse/Input Protection: LM74700-Q1 + DMT6008LFG + SMBJ33CA
Open Layout Checks
