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External + ── mating plug ── J1.1 ── F1 ── reverse-polarity protection ── VIN_PROTECTED ── load/regulator
External − ── mating plug ── J1.2 ────────────────────────────────────── GND ───────────── return
                                                        TVS and input capacitors connect
                                                        across the appropriate protected rails.

• Required for connection: The PCB header and a manufacturer-confirmed compatible two-position cable plug. An exact mating-plug MPN was not verified; do not order a plug solely because it has 5.08 mm pitch. The header is not the cable's screw-clamp terminal: conductor size, strip length, ferrules, and tightening torque must come from the selected plug's documentation.
• Required passives for the connector itself: None. It is an interconnect and provides no voltage regulation, current limiting, reverse-polarity protection, or surge suppression.
• Application-dependent protection: Select F1 or an electronic current limiter to protect the weakest part of the wire/plug/header/PCB path, considering time-current behavior and fault energy. Use reverse-polarity protection if wiring errors are credible. For transient-exposed cables, select a TVS with a stand-off voltage above the maximum normal rail and a clamp voltage compatible with downstream circuitry; coordinate it with fault protection.
• Application-dependent capacitance: Follow the downstream regulator/load datasheet for ceramic and bulk capacitor values, voltage ratings, and placement. Put the regulator's mandatory input ceramic capacitor close to its VIN/GND pins and keep its high-frequency loop short; cable-entry bulk capacitance may be useful, but no universal 1 µF value is required by this header. Check inrush current if significant capacitance is added.
• Connection procedure: De-energize before mating or unmating. Hot-plug capability, load-break capability, contact sequencing, mating-cycle endurance, and retention force are unverified; do not claim them.

• Footprint and board edge: Use the exact manufacturer drawing to establish hole size, pin geometry, housing outline, and contact numbering. Only the 5.08 mm nominal pitch is confirmed by the distributor listing above. Reserve room for the entire mated plug, withdrawal direction, cable bend, and enclosure opening; do not infer a board-edge offset from pitch alone. This guide does not certify the existing Flux footprint.
• High-current copper: Size both supply and return paths from current, actual copper thickness, layer, acceptable temperature rise, and voltage drop. Use short, wide copper paths or pours and eliminate narrow necks at pads and vias. A connector's 10 A UL rating does not establish that an arbitrary PCB trace or via can carry 10 A; validate the assembled board at worst-case load and ambient. No universal trace width is asserted here.
• Thermal relief and soldering: Balance solderability against electrical/thermal resistance. Where reliefs are used, size their combined spokes for the path current; avoid a high-current pad feeding a large plane through thin spokes. Direct plane attachment may require more controlled heat input. Qualify hole fill and the actual soldering process against the +250 °C/5-second maximum.
• Insulation and mechanical loads: Set PCB creepage and clearance from the end-product standard, working voltage, pollution degree, overvoltage category, and altitude—not just connector pitch or the 300 V rating. Keep unrelated copper out of the cable-entry area and provide strain relief so cable loads do not repeatedly stress the solder joints.
• Local circuit layout: Place protection and entry filtering to control the exposed cable path, while retaining regulator-required decoupling at the regulator. This connector does not impose differential-pair rules and is not a characterized controlled-impedance interface; do not assume suitability for high-speed differential links without a separate signal-integrity evaluation.

1. Assuming equal pitch means interchangeable connectors. Housing profile, contact engagement, polarization, pin size, solder-tail length, and PCB datum offsets can differ. Reversing a footprint or plug view can also reverse DC polarity. Check original drawings and a mated sample, map both contacts by continuity, and label the board and harness consistently.
2. Treating headline ratings as unconditional system capability. The datasheet distinguishes UL 10 A/300 V and IEC 15 A/320 V. The mating plug, cable, copper, relief spokes, ambient conditions, and safety requirements can impose lower limits. Do not use dielectric withstand as a working-voltage rating, assume rated current at the temperature endpoint, or treat the header as a load-break switch.

• KANGNEX manufacturer drawing, distributor-hosted: WJ2EDGRC-5.08 family / C3697 PDF. Drawing title “PLUG-IN TERMINAL BLOCK,” WJ2EDGRC-5.08-XXP-1Y-00A. Revision A, dated 2024.03.10. Used for electrical/test ratings, temperature, and soldering limit. The filename upload timestamp is not the drawing revision date. A manufacturer-direct hosted copy was not located; the accessible copy is hosted by LCSC.
• LCSC, primary distributor listing: KANGNEX WJ2EDGRC-5.08-02P-14-00A, C3697. Used for exact sale identity, positions, nominal pitch, and mounting style. Live page; no document revision/date supplied.
• Phoenix Contact, primary manufacturer product page: 1757242 — MSTBA 2,5/ 2-G-5,08. Used to verify alternative type, positions, pitch, and plug-in orientation. Live page; no document revision/date supplied.
• Weidmüller, primary manufacturer product page: 1514960000 — SL 5.08/02/90B 4.5SN OR BX. Used to verify alternative designation, poles, pitch, orientation, and solder-pin length. Live page; no document revision/date supplied.
• JLCPCB, primary assembly procurement listing: C3697. Used for minimum quantity, full-package label/quantity, and restriction that purchased components remain for future PCBA orders and cannot ship separately. Live page; no document revision/date supplied.