Part Review and Datasheet Validation

flux

I’ll populate every W55RP20 terminal with the datasheet pin description, electrical pin type, and a functional section, then re-read the schematic to verify the properties were applied.

flux

The first batch applied, but Flux warned that some values were non-standard; I’m normalizing them to the accepted Pin Type/Section options as I finish the rest.

flux

Finished. I populated all 69 W55RP20 terminal pins with datasheet-derived Pin Description, standardized Pin Type, and Section, then verified the schematic properties were present.
Open items:
  • I used Flux-standard Pin Type values where needed, e.g. Power In, Power Out, Bi-Directional, Input, Output, and Ground, rather than raw datasheet labels like AO/AI/PWR.
Suggested next steps:
  1. Update the Datasheet URL to the official WIZnet v1.0.2 PDF.
  2. Re-run a final part review/export check before publishing or using this part in designs.
Update datasheet URL
Run final review
Verify footprint geometry
Check publish readiness
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W55RP20 Part Review
Reviewed project
The Datasheet URL property was already populated, so it was not required to update it under the user's rule. However, the current property points to an uploaded PDF that appears to be an older v1.0.0 document, while WIZnet's official documentation search returns v1.0.2 as the current English PDF. Recommended cleanup: replace the Datasheet URL with the official WIZnet v1.0.2 link above.
Key datasheet specs
  • Device type: System-in-Package integrating WIZnet W5500 Ethernet controller with Raspberry Pi RP2040 MCU.
  • CPU: dual ARM Cortex-M0+, up to 133 MHz.
  • Flash: 2 MByte on-chip.
  • SRAM: 264 kB on-chip SRAM in six independent banks.
  • Ethernet: hardwired TCP/IP stack, 10/100 Ethernet PHY/MAC, 8 sockets, TCP/UDP/IPv4/ICMP/ARP/IGMP/PPPoE.
  • USB: USB 2.0 full-speed controller/PHY, host/device support.
  • GPIO: 23 GPIO pins; GPIO26-GPIO29 support ADC0-ADC3.
  • Peripherals: up to 2 UART, 2 SPI, 2 I2C, 16 PWM channels, 12 DMA channels.
  • Operating voltage headline: 1.8 V to 3.3 V; detailed rails include IOVDD/VREG_VIN 1.62–3.63 V, USB_VDD/VDD/AVDD nominal 3.3 V rails, DVDD nominal 1.1 V.
  • Operating temperature: -40 °C to +85 °C.
  • Package: QFN68, 8 mm x 8 mm, 0.40 mm pitch, exposed GND pad listed as pin 69.
  • Package dimensions: pad width b 0.15–0.25 mm, lead length L 0.35–0.45 mm, exposed pad D2/E2 6.15–6.25 mm.
  • Datasheet recommended PCB footprint section: marked TBD, so pad geometry cannot be fully validated against an official recommended land pattern.
Symbol/pin cross-check
The project symbol consists of 69 terminal-style pins, numbered 1 through 69. Pin names and numbering match the datasheet table:
  • 1 TXN, 2 TXP, 3 AVDD, 4 RXN, 5 RXP, 6 AVDD, 7 EXRES1, 8 AVDD.
  • 9 GPIO4, 10 GPIO5, 11 GPIO6, 12 GPIO7, 13 IOVDD, 14 GPIO8, 15 GPIO9, 16 GPIO10, 17 GPIO11, 18 GPIO12, 19 GPIO13, 20 GPIO14, 21 GPIO15.
  • 22 TESTEN, 23 XIN, 24 XOUT, 25 IOVDD, 26 DVDD, 27 SWCLK, 28 SWD, 29 RUN, 30 GPIO16.
  • 31 AVDD, 32 VBG, 33 TOCAP, 34 AVDD, 35 1V2O, 36 SPDLED, 37 LINKLED, 38 DUPLED, 39 ACTLED, 40 GPIO18, 41 GPIO19, 42 VDD, 43 IOVDD, 44 XI, 45 XO.
  • 46 GPIO26/ADC0, 47 GPIO27/ADC1, 48 GPIO28/ADC2, 49 GPIO29/ADC3.
  • 50 PMODE2, 51 PMODE1, 52 PMODE0, 53 IOVDD, 54 ADC_AVDD, 55 VREG_VIN, 56 VREG_VOUT, 57 USB_DM, 58 USB_DP, 59 USB_VDD, 60 IOVDD, 61 DVDD, 62 VDD, 63 BOOT, 64 IOVDD, 65 GPIO0, 66 GPIO1, 67 GPIO2, 68 GPIO3, 69 GND.
Footprint cross-check
  • Project layout contains a footprint with 69 pads, matching QFN68 plus exposed GND pad/pin 69.
  • Datasheet package is QFN68, 8 mm x 8 mm, 0.40 mm pitch, exposed pad 6.2 mm typical.
  • Because the datasheet recommended PCB footprint is TBD, land pattern dimensions cannot be conclusively verified from the datasheet alone.
Mismatches / issues to fix
  1. Pin descriptions are missing in the Flux part. All terminal components have Pin Type: Unspecified and no useful pin description, despite the datasheet providing types and descriptions.
  2. Pin electrical types are not populated. Examples: TXN/TXP are AO, RXN/RXP are AI, power pins are PWR, GND is GND, GPIO pins are I/O, TESTEN/RUN/BOOT/PMODE pins are inputs, LED pins are outputs.
  3. Datasheet URL should ideally be changed to the official WIZnet v1.0.2 PDF rather than the uploaded v1.0.0 PDF currently stored.
  4. Footprint can only be partially verified: pad count matches, but detailed pad sizes/pitch/exposed pad dimensions were not visible in the inspected layout output and the datasheet land pattern section is TBD.
  • Update the part-level Datasheet URL to the official WIZnet v1.0.2 PDF.
  • Populate each pin's Pin Type and Pin Description from Table 3 of the datasheet.
  • If footprint geometry editing/inspection is needed, verify the actual pad pitch, body size, and exposed pad against QFN68 mechanical dimensions or a WIZnet reference footprint, since the datasheet footprint recommendation is TBD.

    Reviewed project

    Key datasheet specs

    Symbol/pin cross-check

    Footprint cross-check

    Mismatches / issues to fix

    Recommended next fixes

Documents

    W55RP20 Part Review

Assets

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W55RP20

W55RP20.stp3D Model
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W55RP20-thumb.png

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W55RP20

W55RP20

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kicad_mod

W55RP20

QFN40P800X800X90-69N-D.kicad_modFootprint

W55RP20

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Ethernet ICs W55RP20 microcontroller, Dual ARM Cortex-M0+ a. 133MHz, 2MByte Flash memory on-chip, 264kB on-chip SRAM in six independent banks, DMA controller
W55RP20 is a highly integrated System-in-Package (SiP) from WIZnet that combines the popular RP2040 dual-core microcontroller with a W5500 hardware TCP/IP Ethernet controller. Designed for IoT, industrial automation, and embedded networking applications, the W55RP20 delivers reliable Ethernet connectivity, low power consumption, and high-performance processing in a compact package. It simplifies Ethernet-enabled designs by integrating the MCU, network stack, flash memory, and Ethernet functionality into a single device.
Key Features Dual-core ARM Cortex-M0+ processor running up to 133 MHz Integrated hardwired TCP/IP stack for reliable Ethernet communication 2 MB on-chip Flash memory 264 KB SRAM in six independent memory banks Built-in 10BASE-T / 100BASE-TX Ethernet MAC and PHY Supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE protocols 23 GPIO pins, including 4 analog-capable inputs 2× UART, 2× SPI, and 2× I²C interfaces 16 PWM channels and 8 Programmable I/O (PIO) state machines USB 1.1 Host/Device controller with integrated PHY 12-channel DMA controller for efficient data transfer Operating voltage range of 1.8 V to 3.3 V Industrial temperature support up to -40°C to +85°C Compact 68-QFN package for space-constrained designs
#W55RP20 #WIZnet #RP2040 #EthernetMCU #IoT #EmbeddedSystems #IndustrialAutomation #TCPIP #EthernetController #Microcontroller #HardwareTCPIP #Networking #EmbeddedDesign #SmartDevices #IoTDevelopment

Properties

W55RP20

WIZnet Inc

Integrated Circuits

docs.wiznet.io/img/products/w55rp20/W55RP20_ds_v100e.pdf

IC

parametric-v1

creativecommons.org/licenses/by/4.0/

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