Pin Function Grouping

adrian95

adrian95

Looking at the datasheet of this component, can you group together pins by their functions? for example for Power, 3v3, gnd_1 gnd_2 etc NOTE: If you group them, can you not add the same pin if you already added them in a group? You should know which pin function is common for its function

flux

I grouped the STM32F405RGT6 LQFP64 pins so each physical pin appears exactly once, using power/ground/control/clock groups plus GPIO port groups to avoid duplicate alternate-function assignments. Full grouping is in STM32F405RGT6 Pin Function Groups.
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STM32F405RGT6 Pin Function Groups
Grouped for the 64-pin LQFP STM32F405RGT6. Each physical pin appears exactly once below.
Grouping rule used
  • Dedicated supply pins are grouped as Power / 3V3 or Ground.
  • Dedicated oscillator pins are grouped as Clock.
  • Dedicated reset/boot pins are grouped as Control / Boot.
  • GPIO-capable pins are grouped by their GPIO port: GPIOA, GPIOB, GPIOC, GPIOD, GPIOH.
  • Pins with alternate functions such as SWD, USB, SPI, I2C, USART, ADC, timers, etc. are not duplicated into multiple groups; their primary grouping here is by GPIO port unless they are dedicated power/control/clock pins.
This follows the Flux part-project grouping guidance: MCU pins should generally use shared prefixes such as PA, PB, PC, etc. for Pin Group, while singleton pins such as NRST and BOOT0 should use their own group. For large IC symbols, power/ground pins should be in a dedicated power sub-symbol, and each pin should belong to exactly one sub-symbol.
Proposed groups

Table

GroupPins
Power / 3V3 digital19 VDD, 32 VDD, 49 VDD
Power / Analog 3V313 VDDA
Power / Backup1 VBAT
Internal regulator caps31 VCAP_1, 48 VCAP_2
Ground / Digital18 VSS, 33 VSS, 50 VSS
Ground / Analog12 VSSA
Clock / Oscillator3 PC14-OSC32_IN, 4 PC15-OSC32_OUT, 5 PH0-OSC_IN, 6 PH1-OSC_OUT
Control / Reset7 NRST
Control / Boot28 PB2/BOOT1, 62 BOOT0
GPIOA14 PA0-WKUP, 15 PA1, 16 PA2, 17 PA3, 20 PA4, 21 PA5, 22 PA6, 23 PA7, 42 PA8, 43 PA9, 44 PA10, 45 PA11, 46 PA12, 47 PA13, 51 PA14, 52 PA15
GPIOB26 PB0, 27 PB1, 29 PB10, 30 PB11, 34 PB12, 35 PB13, 36 PB14, 37 PB15, 57 PB3, 58 PB4, 59 PB5, 60 PB6, 61 PB7, 63 PB8, 64 PB9
GPIOC2 PC13, 8 PC0, 9 PC1, 10 PC2, 11 PC3, 24 PC4, 25 PC5, 38 PC6, 39 PC7, 40 PC8, 41 PC9, 53 PC10, 54 PC11, 55 PC12
GPIOD56 PD2
Pin-count check
  • Total listed pins: 64 / 64
  • Duplicate physical pins: none
Optional alternate grouping if you want schematic functional blocks instead of port blocks
If the goal is a human-readable multi-section MCU symbol rather than GPIO-port grouping, we can instead split the same pins into blocks like:
  • Power
  • Ground
  • Clock
  • Reset/Boot
  • Debug
  • USB
  • Serial buses
  • Analog
  • Remaining GPIO
But that requires deciding which alternate function to prioritize for each multi-function GPIO pin. The table above avoids that ambiguity by grouping each pin by its datasheet pin name / port prefix and ensuring no duplicates.

    Grouping rule used

    Proposed groups

    Pin-count check

    Optional alternate grouping if you want schematic functional blocks instead of port blocks

Documents

    STM32F405RGT6 Pin Function Groups

Assets

STM32F405RGTx

STM32F405RGTx

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step

LQFP-64_10x10mm_P0.5mm.step

3D3D Model
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LQFP-64_10x10mm_P0.5mm.kicad_mod

FOOTPRINT_V5Footprint
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STM32F405RGT6

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ARM® Cortex®-M4 series Microcontroller IC 32-Bit Single-Core 168MHz 1MB (1M x 8) FLASH 64-LQFP (10x10)
Arm® Cortex®-M4 32b MCU+FPU, 210DMIPS, up to 1MB flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces, and camera
Includes ST state-of-the-art patented technology • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memories – Up to 1 Mbyte of flash memory – Up to 192+4 Kbytes of SRAM including 64- Kbyte of CCM (core coupled memory) data RAM – 512 bytes of OTP memory – Flexible static memory controller supporting CompactFlash™, SRAM, PSRAM, NOR and NAND memories • LCD parallel interface, 8080/6800 modes • Clock, reset, and supply management – 1.8 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low-power operation – Sleep, Stop, and Standby modes –VBAT supply for RTC, 20×32-bit backup registers + optional 4 KB backup SRAM • 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input • Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M4 Embedded Trace Macrocell™ • Up to 140 I/O ports with interrupt capability – Up to 136 fast I/Os up to 84 MHz – Up to 138 5 V-tolerant I/Os • Up to 15 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) – Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock – 2 × CAN interfaces (2.0B Active) – SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
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