Function: dual 12-bit voltage-output DAC with SPI interface
Supply voltage: 2.7 V to 5.5 V single supply
Temperature range for E grade: -40 °C to +125 °C
Serial interface: SPI-compatible, up to 20 MHz SCK
Output: rail-to-rail output amplifiers, typical settling time 4.5 µs
Reference inputs: external VREFA and VREFB, range VSS to VDD in unbuffered mode
Gain: selectable 1x or 2x by command bit
Typical operating current: 350 µA at 5 V, 250 µA at 3 V; shutdown current 0.3 µA typical
Package: 14-lead plastic small outline, narrow SOIC, 3.90 mm body, 1.27 mm pitch
Recommended bypass: 0.1 µF ceramic from VDD to VSS; datasheet also recommends optional 10 µF bulk capacitor
Datasheet pinout vs schematic symbol
Table
Pin
Datasheet symbol
Datasheet function
Project terminal
Result
1
VDD
Supply voltage input
VDD
Match
2
NC
No connection
NC
Match
3
CS
Chip select input, active low
~CS
Match; active-low notation is appropriate
4
SCK
Serial clock input
SCK
Match
5
SDI
Serial data input
SDI
Match
6
NC
No connection
NC_2
Match
7
NC
No connection
NC_3
Match
8
LDAC
DAC latch / synchronization input, active low usage
~LDAC
Match; active-low notation is appropriate
9
SHDN
Hardware shutdown input, low = shutdown
~SHDN
Match; active-low notation is appropriate
10
VOUTB
DAC B output
VOUTB
Match
11
VREFB
DAC B reference input
VREFB
Match
12
VSS
Ground reference
VSS
Match
13
VREFA
DAC A reference input
VREFA
Match
14
VOUTA
DAC A output
VOUTA
Match
Footprint review
The project has 14 PCB pads and a default footprint outline consistent with a 14-lead SOIC narrow package. The visible outline corresponds to approximately 3.9 mm body width and 8.65 mm body length, which matches Microchip SL 14-lead SOIC dimensions. The project property currently says Package or Case Code: TO, which does not match the datasheet and should be corrected to SOIC-14 / SL narrow SOIC.
Mismatches / issues flagged
Package property mismatch: project shows Package or Case Code: TO; datasheet says SL = 14-Lead Plastic Small Outline - Narrow (SOIC). This should be corrected.
Datasheet property source: a datasheet URL exists, but it points to an uploaded PDF rather than Microchip's official PDF URL. Since the user instruction only required updating if no datasheet URL was set, I did not change the part-level property. Recommended official URL: https://ww1.microchip.com/downloads/en/DeviceDoc/22250A.pdf
Pin electrical types are all Unspecified on the terminals. Functionally the pin numbers/names match, but better metadata would set VDD as Power In, VSS as Ground, VOUTA/VOUTB as Output, VREFA/VREFB and digital control/SPI pins as Input, and NC pins as Not Connected.
Pin descriptions are not populated beyond terminal names. Adding datasheet-derived pin descriptions would improve library quality.
Overall result
Symbol pin numbering and names match the official datasheet. Footprint pad count and outline appear consistent with the required 14-lead narrow SOIC package. Main corrections recommended are metadata-level: package property should not be TO, and pin types/descriptions should be enriched.