Part Information Review and Update

I reviewed the part against the existing project data and the official Analog Devices datasheet already linked in the project, so no web lookup or datasheet-property update was needed.
Part metadata check

Table


FieldIn projectIn datasheetResult
ManufacturerAnalog DevicesAnalog DevicesMatch
MPNMAX96724RGTN/V+MAX96724RGTN/V+Match
Datasheet URLhttps://www.analog.com/MAX96724R/datasheetOfficial Analog Devices datasheet landing pageMatch
Description"Quad Tunneling GMSL2/1 to CSI-2 Deserializer Ordering Information"Quad GMSL2/1 to CSI-2 deserializerMostly match, but project description looks like ordering text rather than the clean device description
Package / case codeTO56-pin TQFN-EP, package code T5688; also 56-pin TQFN-SW, package code T5688YMismatch
Key specs from the datasheet

Table


CategoryDatasheet value
FunctionQuad GMSL2/1 deserializer to 1, 2, or 4 MIPI D-PHY or C-PHY outputs
Forward link rates3 Gbps or 6 Gbps per GMSL2 link
Reverse link rate187.5 Mbps for GMSL2
MIPI supportD-PHY v1.2 up to 2.5 Gbps/lane, C-PHY v1.0 up to 5.7 Gbps/lane
InputsUp to 4 GMSL links
Temperature grade-40 C to +105 C ambient for MAX96724RGTN/V+
Package56-pin TQFN-EP, small 8 x 8 mm package
Supply railsVTERM 1.14 V to 1.26 V, VDD18 1.7 V to 1.9 V, VDD 0.95 V to 1.05 V or 1.14 V to 1.26 V, VDDIO 1.7 V to 3.6 V
Symbol and pin-count cross-check

Table


CheckResult
Main numbered pinsSymbol includes pins 1 through 56
Exposed padSymbol also includes EP
Total electrical contacts57 terminals in the project = 56 numbered pins + exposed pad
Pin namingCore names align well with the datasheet naming for the R variant
Variant handlingThe symbol correctly uses N.C. entries for pins 43 to 54 for the MAX96724R variant
Pin-description cross-check

Table


AreaDatasheet expectationIn symbolResult
GMSL serial linksSIOA/B/C/D differential pairsPresentMatch
Multifunction pinsMFP0-MFP8 with shared functionsPresent, including combined labels like CFG1/MFP6, SDA1/MFP7, SCL1/MFP8Match
Control/miscCFG0, PWDNB, SDA, SCL, X1/OSC, X2, XRESPresentMatch
PowerVDD18, VDDIO, VDD, VTERM, CAP_VDD, EPPresentMatch
R-variant upper CSI outputsPins 43-54 may be N.C. for MAX96724RImplemented as N.C. padsMatch
Footprint cross-check

Table


CheckResult
Footprint existsYes
Pad countFootprint has pads corresponding to all symbol terminals, including EP
Pad naming consistencyPad names match the symbol terminal names
Package metadata consistencyNot consistent with datasheet because project package property says TO, while datasheet package is 56-pin TQFN-EP / TQFN-SW
Issues flagged

Table


SeverityIssueNotes
HighPackage/Case Code property is wrongTO does not match the datasheet package. It should reflect 56-pin TQFN-EP and ideally package code T5688 or T5688Y, depending intended footprint variant.
MediumDescription is not cleanly normalizedCurrent description reads like ordering-info text rather than a concise part description.
MediumPin functional metadata is incomplete in-projectAll terminals are currently typed as Pin Type: Unspecified and there are no rich in-project pin descriptions, even though the symbol names themselves are mostly correct.
LowFootprint geometry not fully verified from current layout inspect outputI could confirm existence, pad naming, and pad count, but not full mechanical dimensions from the current layout data alone.
Bottom line

Table


CategoryVerdict
MPNGood
Datasheet linkGood
Pin countGood
Symbol namingGood overall
R-variant pin mappingGood
Footprint pad presenceGood
Package propertyNeeds correction
Rich pin descriptions/propertiesCould be improved
The only clear hard mismatch I found is the package metadata. The symbol itself appears substantially consistent with the MAX96724R datasheet, including the 56 + EP terminal structure and the N.C. treatment for pins 43-54 on the R variant.
Fix package metadata
Add pin descriptions
Check footprint dimensions

No files yet

Documents

    Documents are markdown text files which describe project goals, capture details, or even simulation outputs.

    Assets

    MAX96724RGTN_V+

    QFN50P800X800X80-57N.kicad_modFootprint
    MAX96724RGTNV+-thumb.png

    MAX96724RGTNV+-thumb.png

    MAX96724RGTNV+-thumbThumbnail

    MAX96724RGTN_V+

    MAX96724RGTN_V+ Symbol.svgDefault
    MAX96724RGTN_V+

    MAX96724RGTN_V+

    MAX96724RGTN_V+.stp3D Model

    MAX96724RGTN/V+

    MAX96724RGTN/V+ thumbnail
    6Gbps Deserializer 4 Input 2 Output 56-TQFN (8x8) #CommonPartsLibrary #IntegratedCircuit

    Properties

    MAX96724RGTN/V+

    Analog Devices

    Integrated Circuit

    IC

    TO

    Pricing & Availability

    DPN

    Stock

    Qty 1

    3

    0–24

    $16.29–$24.79

    1

    3

    $33.4182

    1

    304

    $26.18

    1

    24

    $16.29

    Controls