Part Data Review and Validation
CHGIN_*, BST1, BST2SYS_*, BATT_*, PVL, AVLGND_*, PGND_*LX1_*, LX2_* as PassiveInput, Bi-Directional, or Open Collector as appropriatePin Description metadata to every pinDISQB_AT appears to represent datasheet pin DISQBAT; I left the designator unchanged and noted that in its pin description.DISQB_AT to the datasheet pin name DISQBAT, then verify the symbol metadata still maps it to bump G2.DISQB_AT to DISQBAT to match the datasheet.G2InputDISQBAT battery-discharge control input.MAX77962EWJ12+T against the official Analog Devices / Maxim MAX77962 product information and datasheet source.Pin Type fields are currently Unspecified._1, _2, _3, _4, _5, which is acceptable in Flux for unique terminal designators, provided the Pin Number property maps each one to the correct WLP bump.Table
| Bump | Current terminal | Current section | Review |
|---|---|---|---|
| A1 | BST1 | Switching / Power Stage | OK. Bootstrap/driver supply belongs with switching stage. |
| A2 | CSINN | Battery / Charging | Functionally input current-sense negative. Better section: Power Input / Current Sense. |
| A3 | CSINP | Battery / Charging | Functionally input current-sense positive. Better section: Power Input / Current Sense. |
| A4 | PVL | Configuration / Programming | Likely internal/bypass/supply-related pin, not configuration. Better section: Bias / Bypass / Supply. |
| A5 | AVL | Configuration / Programming | Likely internal/bypass/supply-related pin, not configuration. Better section: Bias / Bypass / Supply. |
| A6 | ITO | Configuration / Programming | OK. Programming/config pin. |
| A7 | VSET | Configuration / Programming | OK. Programming/config pin. |
| B1 | CHGIN_1 | Power Input | OK. |
| B2 | CHGIN_2 | Power Input | OK. |
| B3 | CHGIN_3 | Power Input | OK. |
| B4 | CHGIN_4 | Power Input | OK. |
| B5 | STBY | Status / Control | OK. Control pin. |
| B6 | ISET | Configuration / Programming | OK. |
| B7 | INLIM | Configuration / Programming | OK. |
| C1 | LX1_1 | Switching / Power Stage | OK. |
| C2 | LX1_2 | Switching / Power Stage | OK. |
| C3 | LX1_3 | Switching / Power Stage | OK. |
| C4 | LX1_4 | Switching / Power Stage | OK. |
| C5 | GND_1 | Ground | OK. |
| C6 | GND_2 | Ground | OK. |
| C7 | GND_3 | Ground | OK. |
| D1 | PGND_1 | Ground | OK. Power ground grouped with grounds; alternatively separate Power Ground. |
| D2 | PGND_2 | Ground | OK. |
| D3 | PGND_3 | Ground | OK. |
| D4 | PGND_4 | Ground | OK. |
| D5 | BATSP | Battery / Charging | OK. Battery differential sense positive. |
| D6 | GND_4 | Ground | OK. |
| D7 | INTB | Status / Control | OK. |
| E1 | LX2_1 | Switching / Power Stage | OK. |
| E2 | LX2_2 | Switching / Power Stage | OK. |
| E3 | LX2_3 | Switching / Power Stage | OK. |
| E4 | SYS_1 | System Power | OK. |
| E5 | BATT_1 | Battery / Charging | OK. |
| E6 | SYSA | System Power | OK. Analog/system sense or supply pin belongs with system power. |
| E7 | INOKB | Status / Control | OK. |
| F1 | SYS_2 | System Power | OK. |
| F2 | SYS_3 | System Power | OK. |
| F3 | SYS_4 | System Power | OK. |
| F4 | SYS_5 | System Power | OK. |
| F5 | BATT_2 | Battery / Charging | OK. |
| F6 | STAT | Status / Control | OK. |
| F7 | SDA | I2C Communication | OK. Datasheet identifies SDA as serial I2C data. |
| G1 | BST2 | Switching / Power Stage | OK. Bootstrap/driver supply belongs with switching stage. |
| G2 | DISQB_AT | System Power | Mismatch: name appears split/typo. Datasheet/product snippets and EV kit collateral refer to DISQBAT; rename terminal to DISQBAT unless the official pin table explicitly shows otherwise. Section should be Status / Control or Battery/System control, not pure System Power. |
| G3 | OTGEN | USB OTG | OK, though this can also be grouped under Status / Control because it is an enable/control input for OTG/reverse buck mode. |
| G4 | BATSN | Battery / Charging | OK. Battery differential sense negative. |
| G5 | BATT_3 | Battery / Charging | OK. |
| G6 | THM | Thermal / Monitoring | OK. Could also be grouped with Battery / Charging because this is the battery thermistor/JEITA monitor input. |
| G7 | SCL | I2C Communication | OK. Datasheet identifies SCL as serial I2C clock input. |
Power Input / Current Sense and move CSINP and CSINN there. These are input current-sense pins, not battery terminals.Bias / Bypass / Internal Supplies and move PVL and AVL there. They are not configuration/programming pins.DISQB_AT to DISQBAT if permitted by the parametric-symbol naming rules. This is the clearest mismatch found.Power Ground section for PGND_1 through PGND_4 while keeping GND_1 through GND_4 in Ground or Signal Ground.OTGEN can remain in USB OTG, but grouping it with Status / Control is also reasonable.THM can remain in Thermal / Monitoring, but its design context is battery thermistor / JEITA monitoring, so Battery / Charging is also acceptable.21-100400.pdf for final land-pattern dimensional verification.Unspecified. For a high-current charger IC, pin type metadata should be improved to support ERC and review quality:CHGIN_*, SYS_*, SYSA, BATT_*, PVL, AVL, BST1, BST2, LX1_*, LX2_*: Power or Passive/Special power-stage pins, depending on Flux pin-type options.GND_*, PGND_*: Ground / Power Ground.SCL, SDA: Digital input / bidirectional open-drain style I2C pins.INTB, INOKB, STAT: Open-drain/status outputs if confirmed by datasheet.STBY, OTGEN: Digital inputs/control pins.ISET, INLIM, ITO, VSET, THM, CSINP, CSINN, BATSP, BATSN: Analog/config/sense pins.Pin Number mapping from the project.A1 BST1, A3 CSINP, F7 SDA, and G7 SCL.G2 DISQBAT and the exact behavior/type of status/control pins.Welcome 👋
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