Part Data Review and Validation

flux

I’ll update the existing terminal pin metadata in-place, using the datasheet-derived functions from the previous review and then verify the properties were applied.

flux

Set and verified pin types for all 49 MAX77962EWJ12+T terminals.
Summary:
  • Power inputs: CHGIN_*, BST1, BST2
  • Power outputs: SYS_*, BATT_*, PVL, AVL
  • Grounds: GND_*, PGND_*
  • Switching nodes: LX1_*, LX2_* as Passive
  • I2C/control/sense pins: set to Input, Bi-Directional, or Open Collector as appropriate
  • Added concise Pin Description metadata to every pin
One naming issue remains from the prior review: DISQB_AT appears to represent datasheet pin DISQBAT; I left the designator unchanged and noted that in its pin description.
A

adrian95

Fix DISQB_AT to match the datasheet pin name DISQBAT.

flux

I’ll rename the existing terminal from DISQB_AT to the datasheet pin name DISQBAT, then verify the symbol metadata still maps it to bump G2.

flux

Renamed DISQB_AT to DISQBAT to match the datasheet.
Verified the terminal still has:
  • Pin Number: G2
  • Pin Type: Input
  • Pin Description: DISQBAT battery-discharge control input.
Check DISQBAT
Find pin mismatches
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Preview

MAX77962EWJ12+T Parametric Symbol Review
Scope
Reviewed the current parametric symbol terminal metadata and footprint pad count for MAX77962EWJ12+T against the official Analog Devices / Maxim MAX77962 product information and datasheet source.
Official datasheet URL added to the project properties:
https://www.analog.com/media/en/technical-documentation/data-sheets/max77962.pdf
Official product page confirms:
  • Manufacturer: Analog Devices / Maxim Integrated
  • MPN: MAX77962EWJ12+T
  • Function: 23 VIN, 3.2 AOUT USB-C buck-boost charger with Smart Power Selector for 2-cell Li-ion batteries
  • Package: WLCSP / 49-bump WLP
  • Body size: 3.458 mm x 3.458 mm
  • Package drawing: https://mds.analog.com/api/public/content/21-100400.pdf
Current project observations
  • Schematic symbol is implemented as 49 terminal pins.
  • Footprint contains 49 pads.
  • Board setup has no routed nets and no component instance in the BOM; this appears to be a part/symbol/footprint project, not a populated schematic design.
  • All terminal Pin Type fields are currently Unspecified.
  • Several duplicate electrical pins use suffixes such as _1, _2, _3, _4, _5, which is acceptable in Flux for unique terminal designators, provided the Pin Number property maps each one to the correct WLP bump.
Pin map reviewed from the current symbol

Table

BumpCurrent terminalCurrent sectionReview
A1BST1Switching / Power StageOK. Bootstrap/driver supply belongs with switching stage.
A2CSINNBattery / ChargingFunctionally input current-sense negative. Better section: Power Input / Current Sense.
A3CSINPBattery / ChargingFunctionally input current-sense positive. Better section: Power Input / Current Sense.
A4PVLConfiguration / ProgrammingLikely internal/bypass/supply-related pin, not configuration. Better section: Bias / Bypass / Supply.
A5AVLConfiguration / ProgrammingLikely internal/bypass/supply-related pin, not configuration. Better section: Bias / Bypass / Supply.
A6ITOConfiguration / ProgrammingOK. Programming/config pin.
A7VSETConfiguration / ProgrammingOK. Programming/config pin.
B1CHGIN_1Power InputOK.
B2CHGIN_2Power InputOK.
B3CHGIN_3Power InputOK.
B4CHGIN_4Power InputOK.
B5STBYStatus / ControlOK. Control pin.
B6ISETConfiguration / ProgrammingOK.
B7INLIMConfiguration / ProgrammingOK.
C1LX1_1Switching / Power StageOK.
C2LX1_2Switching / Power StageOK.
C3LX1_3Switching / Power StageOK.
C4LX1_4Switching / Power StageOK.
C5GND_1GroundOK.
C6GND_2GroundOK.
C7GND_3GroundOK.
D1PGND_1GroundOK. Power ground grouped with grounds; alternatively separate Power Ground.
D2PGND_2GroundOK.
D3PGND_3GroundOK.
D4PGND_4GroundOK.
D5BATSPBattery / ChargingOK. Battery differential sense positive.
D6GND_4GroundOK.
D7INTBStatus / ControlOK.
E1LX2_1Switching / Power StageOK.
E2LX2_2Switching / Power StageOK.
E3LX2_3Switching / Power StageOK.
E4SYS_1System PowerOK.
E5BATT_1Battery / ChargingOK.
E6SYSASystem PowerOK. Analog/system sense or supply pin belongs with system power.
E7INOKBStatus / ControlOK.
F1SYS_2System PowerOK.
F2SYS_3System PowerOK.
F3SYS_4System PowerOK.
F4SYS_5System PowerOK.
F5BATT_2Battery / ChargingOK.
F6STATStatus / ControlOK.
F7SDAI2C CommunicationOK. Datasheet identifies SDA as serial I2C data.
G1BST2Switching / Power StageOK. Bootstrap/driver supply belongs with switching stage.
G2DISQB_ATSystem PowerMismatch: name appears split/typo. Datasheet/product snippets and EV kit collateral refer to DISQBAT; rename terminal to DISQBAT unless the official pin table explicitly shows otherwise. Section should be Status / Control or Battery/System control, not pure System Power.
G3OTGENUSB OTGOK, though this can also be grouped under Status / Control because it is an enable/control input for OTG/reverse buck mode.
G4BATSNBattery / ChargingOK. Battery differential sense negative.
G5BATT_3Battery / ChargingOK.
G6THMThermal / MonitoringOK. Could also be grouped with Battery / Charging because this is the battery thermistor/JEITA monitor input.
G7SCLI2C CommunicationOK. Datasheet identifies SCL as serial I2C clock input.
Section organization verdict
The symbol organization is mostly correct and electrically usable. Recommended refinements:
  1. Create or rename a section to Power Input / Current Sense and move CSINP and CSINN there. These are input current-sense pins, not battery terminals.
  2. Create Bias / Bypass / Internal Supplies and move PVL and AVL there. They are not configuration/programming pins.
  3. Rename DISQB_AT to DISQBAT if permitted by the parametric-symbol naming rules. This is the clearest mismatch found.
  4. Consider a separate Power Ground section for PGND_1 through PGND_4 while keeping GND_1 through GND_4 in Ground or Signal Ground.
  5. OTGEN can remain in USB OTG, but grouping it with Status / Control is also reasonable.
  6. THM can remain in Thermal / Monitoring, but its design context is battery thermistor / JEITA monitoring, so Battery / Charging is also acceptable.
Footprint/package verdict
  • The project footprint has 49 pads, matching the official 49-bump WLP / WLCSP package.
  • Package size in the project description, 3.46 mm x 3.46 mm, matches the official 3.458 mm x 3.458 mm rounded value.
  • I could not verify pad pitch, ball diameter, or exact pad geometry from the current layout summary because only pad count/designators were exposed in the inspected layout data. Use the official package drawing 21-100400.pdf for final land-pattern dimensional verification.
Pin type metadata issue
All pins are currently marked Unspecified. For a high-current charger IC, pin type metadata should be improved to support ERC and review quality:
  • CHGIN_*, SYS_*, SYSA, BATT_*, PVL, AVL, BST1, BST2, LX1_*, LX2_*: Power or Passive/Special power-stage pins, depending on Flux pin-type options.
  • GND_*, PGND_*: Ground / Power Ground.
  • SCL, SDA: Digital input / bidirectional open-drain style I2C pins.
  • INTB, INOKB, STAT: Open-drain/status outputs if confirmed by datasheet.
  • STBY, OTGEN: Digital inputs/control pins.
  • ISET, INLIM, ITO, VSET, THM, CSINP, CSINN, BATSP, BATSN: Analog/config/sense pins.
Key specs from official product information
  • Input operating range: 3.5 V to 23 V.
  • Input withstand: 30 VDC.
  • Output/charge capability: up to 3.2 A buck-boost charger output/charge current.
  • Reverse buck / OTG support: 5.1 V / 1.5 A.
  • Switching frequency options: 600 kHz or 1.2 MHz.
  • Battery support: 2-cell Li-ion use case per product collateral.
  • Integrated Smart Power Selector with instant-on system power path.
  • Supports I2C configuration and resistor-programmed autonomous operation.
  • JEITA-compliant NTC thermistor monitoring.
Limitations
The official Analog Devices PDF URL was found and set, but the automated PDF text extraction did not return the full pin-description table in this session. The review therefore uses:
  • Current symbol terminal Pin Number mapping from the project.
  • Official Analog Devices product page data.
  • Search-result excerpts from the official datasheet confirming representative pins such as A1 BST1, A3 CSINP, F7 SDA, and G7 SCL.
For final signoff, manually open the official PDF pin-description table and confirm every bump assignment A1 through G7, especially G2 DISQBAT and the exact behavior/type of status/control pins.

  • Scope

  • Current project observations

  • Pin map reviewed from the current symbol

  • Section organization verdict

  • Footprint/package verdict

  • Pin type metadata issue

  • Key specs from official product information

  • Limitations