Independent read-only review confirmed 13 active mapped electrical pads, correct peripheral geometry, preserved exposed GND pin 13, and four inactive paste-only artifacts in this source project. It could not verify exact-UID override propagation, consuming-board DRC/routing, or exported stencil apertures. Source repair is verified, but the original placed-board issue is not yet proven resolved. An internal part-quality ticket was filed for Flux engineering review. The consuming board project URL is needed to continue board-instance validation; do not approve manufacturing until paste export is verified.
Scope and status
Project: LT3652EDD#PBF, /adrian95/lt3652eddpbf . Current source part UID returned by datasheet query: 82beb0ca-02bf-490f-9459-0f99b65b43b3.
Completed: inspection and classification of the four reported MH1–MH4 features. They are not thermal vias or mounting holes: FOOTPRINT_V5 contains four unnumbered smd rect pads on F.Paste only, with no drill and no copper layers. Flux generated these as electrical Pad nodes under Mounts.
Completed: source-project rule removes those four erroneous active electrical representations. All 13 real pads, their dimensions/positions, all schematic terminals, and pin numbering remain unchanged. No arbitrary net was assigned and no check was suppressed.
Failed / unavailable: board overlap, invalid-pad and airwire verification: these validators return no result in this part-only project, both before and after. This is not a zero-DRC claim.
Unattempted: board instance update, routing feasibility rerun, stencil/Gerber validation, and publication. No publish operation was exposed by tool discovery. Lead must arrange publication and downstream board verification before closing the overall issue.
Root cause
Imported footprint is Package_DFN_QFN:DFN-12-1EP_3x3mm_P0.45mm_EP1.66x2.38mm. Its main pad 13 is (pad 13 smd rect (at 0 0) (size 1.66 2.38) (layers F.Cu F.Mask)); four surrounding source records are (pad "" smd rect ... (size 0.64 1) (layers F.Paste)). Each lies completely inside the main GND copper extent. They describe stencil windows, not conductive thermal features, so mapping them to arbitrary GND nets or inventing drill holes would misrepresent their purpose.
The datasheet identifies exposed pad 13 as ground reference and backside thermal connection and requires soldering it to the PCB ground plane. The DD recommended land is 2.38 ±0.05 mm × 1.65 ±0.05 mm at 0.45 mm peripheral pitch; existing 1.66 × 2.38 mm land and 0.45 mm pitch were retained.
Exact change
Created ruleset 9c7873b8-8bff-499a-a8fb-b99904cc8440, Remove imported paste-only mounting artifacts. Four exact UID selectors set active: false. This removes physical/electrical geometry rather than hiding a review finding. No !important or DRC waiver added. The asset itself was not edited.
All four UIDs share prefix 6293a98a-acf5-4bc7-837d-55972de31114.defaultFootprint.mounts.. Append the suffix below for the full identifier. The source view does not expose labels MH1–MH4, so their ordering cannot be reliably correlated to those board labels.
Table
UID suffix
Source-project position X,Y (mm, Y-up)
Size (mm)
Before
After
Mapping
15c9c2b98f5f8fc54989d2bd6e884ce9
+0.415, -0.595
0.64 × 1.0
active Pad under Mounts
inactive Pad under Mounts
none, unchanged
64e4336c14b0d112b6cdf5bbc5f39317
-0.415, -0.595
0.64 × 1.0
active Pad under Mounts
inactive Pad under Mounts
none, unchanged
9aac5c4458aff32be2f2c8e74d441bf5
+0.415, +0.595
0.64 × 1.0
active Pad under Mounts
inactive Pad under Mounts
none, unchanged
21f1147f204b4e3b936cd9b0695d0eac
-0.415, +0.595
0.64 × 1.0
active Pad under Mounts
inactive Pad under Mounts
none, unchanged
A direct delete attempt made no changes: generated virtual pad UIDs were rejected as not editable layout node UIDs. The source selector ruleset succeeded and matched exactly four pads. Final readback confirms all four computed.active: false; 13 legitimate pads remain computed.active: true. There remain 17 generated Pad objects in the tree, but only 13 enabled ones.
Preserved electrical mapping and pad identifiers
No board nets exist in this part project; mapping is by schematic terminal Pin Number to numbered footprint pad.
Table
Pin
Terminal
Pad UID
1
VIN
058c4816-9e07-4dbb-94e3-3194b9c15120
2
VIN_REG
aa7a02ca-e45c-4f21-9976-e1e648cc42e6
3
~SHDN
e13a890e-e392-41da-9f4c-15fa63d0c1e3
4
~CHRG
6519e1c8-99d3-49ff-8c4d-88a4b76ca6d4
5
~FAULT
510b3300-0090-46e4-b0da-a893a50d220d
6
TIMER
eae25075-30aa-4dbc-95b4-2950ce18140f
7
VFB
5e4b7df4-cc96-44de-a18e-0385db7d6275
8
NTC
85c1a574-7f9e-426d-9ae3-3d4fcb41cd38
9
BAT
a1ef7eee-69ee-4855-8c50-cdf3cd9fa5c5
10
SENSE
c2e5c5cc-1dbf-4d94-b395-b42d46572ace
11
BOOST
348c9299-0763-4a95-9cd7-613d4b013c7a
12
SW
139488c8-989f-44fb-b88d-4376c3190a1d
13
GND
25aa8a40-dd56-485c-a206-261841c0a138
Pins 1–12 retain 0.7 × 0.25 mm lands, column X = ±1.4 mm, Y pitch 0.45 mm. GND remains centered at origin, 1.66 × 2.38 mm. Model, silk, original asset, terminal properties and schematic placement were untouched.
Verification and remaining limitations
Fresh check timestamp: 2026-10-16T06:31:15.257Z. Missing Terminals and Excluded Terminal both report Success, zero errors and warnings. Read-only schematic inspection returns exactly 13 terminals and the mapping above, zero nets/wires. Read-only layout inspection confirms the exact enabled-state changes and unchanged real geometry.
Warning: stencil aperture preservation is not validated. Removing the generated nodes may also remove their paste output; the original source uses no F.Paste on the large GND pad. The part-only 2D paste-layer read renders no footprint geometry, so it cannot resolve this. Do not claim manufacturing readiness: validate the exposed-pad paste in a placed board/export, and if absent, repair paste-layer representation before manufacturing. This is separate from eliminating erroneous copper.
Warning: source UID selector propagation to a published/placed instance still needs downstream confirmation. After publication/update, read the board footprint, ensure only 13 enabled electrical pads and that GND maps to its actual ground net; then rerun DRCOVERLAPPINGPINSDIFFERENTNETS/overlapping-copper and routing feasibility. Do not treat part checks as equivalent.
Internal quality-report brief for lead
Do not file automatically from this executor. Part: LT3652EDD#PBF; link: /adrian95/lt3652eddpbf . Defect: four unnumbered F.Paste-only rectangles imported as enabled, unmapped Mounts Pad nodes inside exposed GND pin 13, causing reported DRCOVERLAPPINGPINSDIFFERENTNETS in a consuming board. Attempted direct deletion was rejected because generated nodes are virtual; exact source selector active:false removal succeeded and preserves the 13 true terminals. Part checks pass; board DRC and paste export require follow-up. This suggests a footprint importer layer-semantics issue, not missing thermal-via net mapping.