I’ve verified the core wiring requirements, including the unusually small 2.2 nF bootstrap capacitor and the required feedback-ripple network. I’m finishing the alternatives and sourcing sections, with any unresolved compatibility claims clearly labeled.
The Texas Instruments LM5013DDAR is a 100-V, 3.5-A non-synchronous buck DC/DC converter in an 8-pin SO PowerPAD package, intended to step a higher DC supply down to a regulated positive rail. A common integration is a 48-V nominal industrial or telecom supply producing 12 V at up to 3.5 A; TI's typical application targets 300-kHz switching.
This guide covers the LM5013DDAR pinout, buck converter schematic integration, PCB layout, component selection, and purchasing. It is an integration guide, not a validated power-supply design for an unspecified input range or load.
Created and checked the LM5013DDAR Application and Usage Guide in project files, covering all seven requested sections with citations and source links. No drop-in replacement was verified; the guide clearly identifies the verified functional alternative and the second candidate whose datasheet verification remains unresolved.
The Texas Instruments LM5013DDAR is a 100-V, 3.5-A non-synchronous buck DC/DC converter in an 8-pin SO PowerPAD package, intended to step a higher DC supply down to a regulated positive rail. A common integration is a 48-V nominal industrial or telecom supply producing 12 V at up to 3.5 A; TI's typical application targets 300-kHz switching.
This guide covers the LM5013DDAR pinout, buck converter schematic integration, PCB layout, component selection, and purchasing. It is an integration guide, not a validated power-supply design for an unspecified input range or load.
1. Quick Specifications
Absolute maximum ratings are stress limits, not normal design targets. Exceeding them can permanently damage the IC; operation beyond recommended conditions is not implied.
Up to 3.5 A; recommended-conditions table lists 3.0 A nominal. Actual usable load depends on ripple, losses, and cooling.
No separate DC output-current stress rating is established here; do not substitute current-limit trip values.
FB reference
1.181 V minimum, 1.200 V typical, 1.218 V maximum.
FB and RON: −0.3 to 5.5 V relative to GND.
EN/UVLO relative to GND
−0.3 to 100 V.
−0.3 to 100 V.
SW relative to GND
−0.3 to 100 V.
−1.5 to 100 V; minimum −3 V for transients shorter than 20 ns.
BST relative to SW
−0.3 to 5.5 V.
−0.3 to 5.5 V.
BST relative to GND
−0.3 to 105.5 V.
−3 to 105.5 V.
PGOOD relative to GND
−0.3 to 14 V.
−0.3 to 14 V.
Switching frequency
Up to 1000 kHz; programmable on-time 50 to 1000 ns.
Not a separate stress rating.
External bootstrap capacitance
2.2 nF nominal; 1.5 to 2.5 nF permitted.
Datasheet also specifies 1.5 to 2.5 nF in its absolute-maximum table.
Junction temperature, TJ
−40 to +150 °C. This is junction temperature, not an ambient-temperature guarantee.
−40 to +150 °C.
Storage temperature
Not an operating condition.
−65 to +150 °C.
Package
DDA, 8-pin SO PowerPAD plus exposed thermal pad.
Not applicable.
Lead pitch
1.27 mm.
Not applicable.
Thermal resistance
RθJA = 34.8 °C/W; RθJC(bottom) = 1.3 °C/W under the datasheet thermal-test conditions. These are not promises for an arbitrary PCB.
Not a separate stress rating.
Engineering implication: because the recommended VIN ceiling and absolute maximum VIN ceiling are both 100 V, a nominal 100-V supply has no allowance for positive supply tolerance or ringing. Establish a lower normal input ceiling and protection appropriate to the actual surge environment; verify voltage at the IC pins, not just at the connector.
Low-IQ figures must retain their operating-mode conditions: shutdown current is 3.1 µA typical at EN/UVLO = 0 V; sleep current is 10 µA typical under the specified non-switching conditions; active current is 450 µA typical. Do not describe the sleep figure as the current consumption of a switching, loaded converter.
2. Pinout & Connections
Use the DDA top-view pin numbering. The exposed pad may be represented as pad 9 in a CAD library, but TI names it EP; it is not an additional signal pin.
Table
Pin Number
Pin Name
Description
Best Practice
1
GND
Ground for internal circuitry.
Tie directly to the local ground plane and exposed pad; keep switching-current returns out of the FB ground path.
2
VIN
Supply for the high-side MOSFET and internal bias regulator.
Connect to input supply with short, low-impedance routing; place ceramic CIN immediately between VIN and GND.
3
EN/UVLO
Below 1.1 V: shutdown; between 1.1 and 1.5 V: standby; above 1.5 V: startup.
For no external input-UVLO requirement, connect directly to VIN or drive with a logic signal. Otherwise use the datasheet UVLO divider design. Do not leave floating.
4
RON
Sets high-side switch on-time.
Connect RRON to GND, not to VIN; place it close to the IC. RON-to-GND parasitic capacitance must not exceed 20 pF.
5
FB
Voltage-regulation comparator input.
Connect to output-divider midpoint and the selected ripple-injection network; keep this node short and away from SW.
6
PGOOD
Open-drain power-good output.
If used, add a 10 kΩ to 100 kΩ pull-up to a suitable source, typically the receiving logic rail. Do not pull up to high-voltage VIN; the pin limit is 14 V.
7
BST
Floating bootstrap gate-drive supply.
Connect a high-quality 2.2-nF, 50-V X7R capacitor directly between BST and SW. Do not copy a generic 100-nF buck-regulator bootstrap value.
8
SW
High-side MOSFET source / switching node.
Connect to the inductor input, catch-diode cathode, and bootstrap-capacitor return; minimize SW copper area and path length.
EP; CAD pad 9
Exposed pad
No internal electrical connection; thermal interface.
Solder to a grounded thermal land with heat-spreading copper and thermal vias. It must not be left unsoldered.
3. Standard Application Circuit
Power-stage wiring
Connect input positive to VIN and input return to GND. Connect SW through LO to VOUT; place COUT between VOUT and GND. Install an external Schottky catch diode with its cathode at SW and anode at GND: this non-synchronous topology requires the diode to recirculate inductor energy when the high-side MOSFET is off.
Use the following integration checklist:
Input capacitors: TI recommends at least 4.4 µF of high-frequency input capacitance using sufficiently voltage-rated X7S or X7R ceramics. Check effective capacitance under DC bias, not just the printed nominal value, and place the capacitors at VIN/GND. Add bulk capacitance as required by source impedance and cable transients.
Bootstrap capacitor: 2.2 nF, 50 V, X7R between BST and SW, with a short connection. The capacitance limit is unusually restrictive and must be observed.
Inductor: choose ripple current between 30% and 50% of rated load at nominal VIN. The datasheet selection equation is LO = VOUT / (FSW × ΔIL) × (1 − VOUT / VIN(nom)); use consistent SI units. For input transients above 72 V, select at least 22 µH. TI recommends saturation current greater than 7 A; also check RMS heating, DCR, core loss, tolerance, and worst-case ripple at maximum VIN.
Output capacitors: the datasheet uses COUT ≥ ΔIL / (8 × FSW × VOUT(ripple)) and targets capacitive ripple no greater than 0.5% of VOUT. Its 12-V example selects 22 µF, 25 V, X7R; actual required capacitance must also satisfy the system load-transient requirement and DC-bias derating.
Catch diode: reverse breakdown must exceed maximum VIN plus a 25% safety margin. Current capability must exceed maximum DC output current and support the peak current limit. Verify diode dissipation and leakage at elevated temperature.
Output setting, timing, and ripple injection
Connect the top feedback resistor from VOUT to FB and the bottom resistor from FB to quiet GND. TI gives RFB2 = [1.2 V / (VOUT − 1.2 V)] × RFB1, with RFB1 the upper resistor and RFB2 the lower resistor. For the nominal 12-V example, TI uses 453 kΩ upper and 49.9 kΩ lower feedback resistors.
Connect RRON between RON and GND. The datasheet equation is RRON(kΩ) = VOUT(V) × 2500 / FSW(kHz); its nominal 12-V/300-kHz example selects 100 kΩ, 1%. Select RRON so on-time remains greater than 50 ns at maximum VIN. The minimum off timer is 50 ns typical, but is forced to 250 ns when on-time is below 300 ns; therefore, “50-ns on/off time” is not a universally valid operating description.
COT control still requires adequate FB ripple even though no conventional compensation network is needed. The datasheet requires at least 12 mV FB ripple and uses 20 mV as a conservative design figure. Low-ESR ceramic output capacitors alone must not be assumed to provide that ripple.
For the Type 3 ripple-injection circuit, connect RA from SW to a ripple junction, CA from that junction to VOUT, and CB from that junction to FB. TI's example uses RA = 453 kΩ, CA = 3300 pF, and CB = 56 pF, with C0G/NP0 dielectric for CB; these values belong to the documented application and must be re-evaluated when output voltage, frequency, or divider values change.
Define EN/UVLO using VIN, a logic source, or the programmed UVLO divider. If power-good monitoring is needed, pull PGOOD up to the receiving logic supply with a resistor in the documented range.
Example limitations: this guide does not assign a universal inductor value or guarantee 3.5-A delivery across the entire input range. The exact inductor selection in the application drawing could not be consistently verified during extraction, so the documented selection equation and limits are provided instead. Verify startup, line/load regulation, load transients, FB ripple, SW ringing, current limit, and hot-condition temperatures on the finished circuit.
4. PCB Layout & Routing Guidelines
Minimize the high-di/dt loop: place CIN at VIN/GND and the Schottky anode near CIN's return. Keep the IC, diode, and local input-capacitor loop compact; use localized top-side ground connected to GND and the exposed pad.
Control SW area: put the diode and inductor close to SW; keep SW-to-inductor copper short and only wide enough to carry current without excessive heating. Do not make SW a large heat-spreading plane or route it beneath FB.
Provide a real thermal path: solder the exposed pad to its grounded land and use thermal vias to ground planes. For the IC thermal land, avoid narrow thermal-relief spokes that defeat the heat/current path; coordinate stencil aperture and via treatment with assembly. TI requires direct pad soldering and sufficient heat sinking to keep junction temperature below 150 °C.
Size power routing for the actual stackup: use short, thick traces or pours for VIN, VOUT, ground, and diode paths; place COUT near the inductor's VOUT end. No universal millimeter trace width is justified without copper thickness, allowed rise, layer, and via-count information.
Protect analog/timing nodes: place both divider resistors near FB and RRON near RON; sense output at the appropriate load point while keeping the sense route shielded from SW. Keep RON-to-GND parasitics at or below 20 pF. This regulator has no differential signal interface, so differential-pair routing is not applicable.
5. Common Pitfalls / Things to Watch Out For
Copying a generic buck circuit and omitting LM5013-specific details. A generic 100-nF bootstrap capacitor is outside the stated 1.5-to-2.5-nF range, and an all-ceramic output stage without adequate ripple injection can violate the FB ripple requirement. Use the specified 2.2-nF bootstrap capacitor and verify at least 12 mV of correctly phased FB ripple.
Treating 100 V and 3.5 A as unconditional operating promises. Supply overshoot must remain within pin stress limits; the catch diode needs its stated 25% reverse-voltage safety margin, and full-load operation depends on inductor current margin and a soldered, cooled PowerPAD. Do not equate thermal shutdown with an acceptable steady-state temperature.
6. Popular Alternatives & Equivalents
No cross-manufacturer drop-in replacement was verified. A matching SOIC lead count is not evidence of matching pin functions, exposed-pad geometry, bootstrap requirements, feedback reference, or load capability. The following are redesign options, not approved substitutions:
Verified LTC7103 family specifications: 4.4–105 V input, up to 2.3 A output, synchronous buck, 5 × 6 mm UHE QFN.
Functionally similar only; neither pin- nor footprint-compatible. Requires a new schematic and PCB. Its 2.3-A capability is below LM5013's 3.5-A rating. Check exact order-code lifecycle and supply before selecting.
Unverified candidate, not a verified equivalent. The manufacturer datasheet download was blocked and citation-backed extraction of the distributor-hosted copy remained pending. Search material describes a 1-A continuous-load device with a 3.5-A peak switch-current limit, but those values are not treated as verified here.
Potential functional redesign option only. Pin and footprint compatibility have not been verified. Do not mistake a 3.5-A peak current limit for 3.5-A continuous output, or substitute this device based on its exposed-pad SOIC appearance.
The Flux library contains both named candidates, but library availability does not qualify their compatibility. Only one cross-manufacturer alternative could be fully verified in this research; a second verified equivalent is an open sourcing item rather than an invented recommendation.
7. Sourcing & Purchasing Guide
Table
Attribute
Details
Primary Distributors
Buy directly from TI or check exact LM5013DDAR listings at DigiKey and Mouser; both are returned in the library's distributor data. LCSC also has a listing. Confirm distributor authorization and traceability for the chosen purchasing channel.
Packaging Options
LM5013DDAR is DDA, 8 pins, large tape-and-reel. TI also describes quantity-dependent cut-tape and custom-reel fulfillment options; verify what is offered at checkout rather than assuming every carrier is available. See TI ordering details.
Standard MOQ
Full manufacturer reel: 2,500 units, not a generic 3,000-unit reel. Single-unit purchasing is channel-specific: JLCPCB's exact-part listing shows minimum 1 for assembly purchasing, not loose-part shipment. A universal DigiKey/Mouser cut-tape MOQ was not directly verified.
JLCPCB Assembly
Exact listing: LM5013DDAR / C5383001, classified as Extended. The listing states purchased components are held for future PCBA orders and cannot be shipped separately. Recheck current stock, assembly class, fees, and package before committing a BOM.
Ordering-Code Check
Require LM5013DDAR, with DDA PowerPAD package and the specified reel carrier. Do not treat a visually similar plain SOIC footprint as sufficient: the exposed-pad land, paste pattern, and ground/thermal vias matter. Verify any alternative suffix from TI's ordering table.
Sourcing Advice
Prefer TI-direct or confirmed franchised distribution. Require lot/date-code traceability, intact moisture/ESD packaging as applicable, and appropriate inspection for any broker purchase. Non-authorized marketplace stock carries counterfeit, remarking, and handling risks. No stock or price figure in this guide is a purchase guarantee.
Sources
Texas Instruments, LM5013 datasheet, SNVSCB3 — October 2022, the revision identified in the evidence used here. Manufacturer datasheet PDF · Document-number URL. Sections used: device comparison, pin functions, absolute maximum/recommended conditions, thermal/electrical characteristics, COT operation, detailed application design, layout, and package/ordering addendum. The live symlink can change; verify revision before production release.
Texas Instruments, LM5013 product and LM5013DDAR ordering pages: Product · Exact ordering code. No independent page revision date was provided.
Analog Devices, LTC7103 datasheet, Rev. C. Manufacturer PDF · Product page, which lists the Rev. C release as November 18, 2020.
Monolithic Power Systems, MP9486A manufacturer page and datasheet candidate: Product · Manufacturer PDF endpoint · Distributor-hosted manufacturer datasheet. These were sought for alternative qualification; citation-backed verification remains unresolved, so no MPS technical rating is presented as confirmed.
JLCPCB exact-part purchasing listing, a primary source for its own assembly procurement terms: LM5013DDAR / C5383001.
Research date: October 7, 2026. All component values above are tied to documented conditions; unresolved extraction and compatibility items are explicitly identified. No schematic, footprint, or component metadata was changed.