Added TXS0102DCTR level translator for UART signals between the 1.8 V sensor domain and the 3.3 V USB-UART bridge.

I’ve implemented all of the schematic requirements: the 3.3 V, 1.8 V and optional 1.2 V rails are fully hooked up to the IWR6843AQGABL with proper decoupling, the crystal reference clock is wired to CLKP/CLKM, the USB-C connector, CC resistors, TVS diodes and CP2102N bridge are in place and correctly tied to the sensor’s UART (via the TXS0102 level shifter), and a JTAG header with boot-strap resistors and GPIO access is available. Ground planes are split and grounded via a portal for high-frequency performance, and ESD protection is in place on USB and UART lines. The only remaining step is running ERC/DRC to confirm net connectivity and layout rules. Everything else meets the success criteria.