Part Review and Datasheet Verification

Populate all terminal pin types and descriptions from the ISSI datasheet. and fix B1 mismatch
I’ll update the terminal metadata from the ISSI datasheet and correct B1 so the 3.0V BLL variant treats it as RFU/no-connect.
I confirmed the current terminal list: B1 is still labeled CK#, and all 24 terminals need datasheet-derived pin metadata.
Updated all 24 terminal pin types and descriptions from the ISSI datasheet, using Flux-standard pin type values. Fixed the B1 mismatch by renaming CK# to RFU_6 and marking it Not Connected with a BLL-specific RFU description.
Open items:
  • None for the requested metadata update.
Suggested next steps:
  1. Verify the rendered symbol still has the desired visual grouping after CK#RFU_6.
  2. Re-check the footprint pad geometry/pitch before publishing the part.
Verify symbol and footprint
Check visual grouping
Inspect footprint geometry
Run ERC and DRC
Update review document
DQ2
Pin Number
C4
RFU_6
Pin Number
B1
RESET#
Pin Number
A4
DQ0
Pin Number
D3
RWDS
Pin Number
C3
RFU_3
Pin Number
B5
CS#
Pin Number
A3
VSS
Pin Number
B3
RFU_4
Pin Number
C2
DQ7
Pin Number
E1
DQ5
Pin Number
E3
VCCQ_1
Pin Number
D1
DQ6
Pin Number
E2
DQ3
Pin Number
D4
RFU_5
Pin Number
C5
VCCQ_2
Pin Number
E4
DQ1
Pin Number
D2
RFU_2
Pin Number
A5
CK
Pin Number
B2
VCC
Pin Number
B4
VSSQ_2
Pin Number
E5
DQ4
Pin Number
D5
VSSQ_1
Pin Number
C1
RFU_1
Pin Number
A2

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Part Review: IS66WVH64M8DBLL-166B1LI-TR
Reviewed part information
Note: the part already had a Datasheet URL before review, so the existing datasheet property was not required to be populated from scratch. The official ISSI URL should be preferred if project-level Datasheet URL editing is available.
Datasheet key specs
  • Device family: IS66/67WVH64M8DALL/BLL 512Mb HyperRAM
  • Organization: 64M x 8
  • Interface: HyperBus, 8-bit DDR data bus, CS#, CK/CK#, RWDS, RESET#
  • Voltage variant for BLL: 3.0V device; VCC/VCCQ operating range 2.7V to 3.6V
  • Speed grade: 166MHz for this MPN
  • Package: B1 = 24-ball TFBGA, 6mm x 8mm body, 5 x 5 ball array, 1.0mm pitch
  • Temperature code: I = Industrial, -40°C to +85°C
  • Compliance: green/RoHS, halogen-free, TSCA compliant per datasheet ordering information
  • Active read current at 3.6V, 200MHz: max 40mA
  • Active write current at 3.6V, 200MHz: max 35mA
  • Standby current over -40°C to +85°C: max 1500µA; +105°C grade max 1800µA
  • Reset current: max 20mA
  • Power-up wait: up to 150µs from VCC/VCCQ valid and RESET# high to first access
Symbol / terminal cross-check
Project terminals present:
  • Control/clock: CS# A3, RESET# A4, CK B2, CK# B1
  • Data/strobe: DQ0 D3, DQ1 D2, DQ2 C4, DQ3 D4, DQ4 D5, DQ5 E3, DQ6 E2, DQ7 E1, RWDS C3
  • Power: VCC B4, VCCQ D1/E4, VSS B3, VSSQ C1/E5
  • RFU: A2, A5, B5, C2, C5
Datasheet-confirmed signal descriptions:
  • CS#: slave input chip select, active low
  • CK/CK#: clock input; differential clock optional, single-ended CK supported
  • DQ[7:0]: bidirectional command/address/data bus
  • RWDS: bidirectional read/write data strobe and write data mask
  • RESET#: input with internal weak pull-up
  • VCC: array/core power
  • VCCQ: I/O power; must be same voltage as VCC
  • VSS/VSSQ: grounds
  • RFU: no-connect/reserved; leave unconnected and do not use as routing channel
Footprint cross-check
  • Footprint pad count: 24 pads present in layout.
  • Datasheet package: 24-ball FBGA/TBGA-style 5x5 array with one missing ball site, 1.0mm pitch, 6mm x 8mm body.
  • Layout shows a BGA-style body outline and 24 pad nodes. The available flat layout rendering did not expose each pad center/diameter, so the exact 1.0mm pitch and ball diameter were not fully machine-verified from the layout data.
Mismatches / issues flagged
  1. B1 assignment mismatch for this exact BLL 3.0V part: the datasheet note states B1 is CK# on the 1.8V device, but B1 is RFU on the 3.0V device. The project currently defines B1 as CK#. For IS66WVH64M8DBLL-166B1LI-TR, B1 should be treated as RFU/no-connect unless ISSI provides a variant-specific drawing contradicting this note.
  2. Pin descriptions are missing: all terminals show Pin Type: Unspecified and no Pin Description property. These should be populated from Table 3.1: input, bidirectional I/O, power, ground, or no-connect/RFU.
  3. Datasheet URL is distributor-hosted: the existing project Datasheet URL points to Mouser. An official ISSI PDF exists and should be preferred for the Datasheet URL when editing the part-level property is available.
  4. RFU handling should be explicit: RFU balls should be named/typed as no-connect and documented as “leave unconnected; do not route through for future compatibility.”
  5. Footprint dimensions only partially verified: pad count and body outline are consistent with 24-ball 6mm x 8mm package, but exact pad positions/pitch were not visible in the layout inspection output.
  • Rename/reclassify B1 from CK# to an RFU/no-connect terminal for the BLL 3.0V part, or verify with ISSI if differential clock on B1 is actually bonded for this ordering code.
  • Populate Pin Type and Pin Description for every terminal based on datasheet Table 3.1.
  • Prefer the official ISSI datasheet URL: https://www.issi.com/WW/pdf/66-67WVH64M8DALL-BLL.pdf
  • Re-run footprint inspection with detailed pad geometry visible before publishing, confirming 5x5 1.0mm-pitch array and 6mm x 8mm body.
  • Reviewed part information

  • Datasheet key specs

  • Symbol / terminal cross-check

  • Footprint cross-check

  • Mismatches / issues flagged

  • Recommended corrections

Documents

  • Part Review: IS66WVH64M8DBLL-166B1LI-TR

Assets

stp

IS66WVH64M8DBLL-166B1LI-TR

IS66WVH64M8DBLL-166B1LI-TR.stp3D Model
IS66WVH64M8DBLL-166B1LI-TR

IS66WVH64M8DBLL-166B1LI-TR

IS66WVH64M8DBLL-166B1LI-TR Symbol.svgDefault
IS66WVH64M8DBLL-166B1LI-thumb.png

IS66WVH64M8DBLL-166B1LI-thumb.png

IS66WVH64M8DBLL-166B1LI-thumbThumbnail
kicad_mod

IS66WVH64M8DBLL-166B1LI-TR

BGA24C100P5X5_600X800X120.kicad_modFootprint

IS66WVH64M8DBLL-166B1LI

IS66WVH64M8DBLL-166B1LI thumbnail
PSRAM (Pseudo SRAM) Memory IC 512Mbit HyperBus 166 MHz 36 ns 24-TFBGA (6x8)
The IS66/67WVH64M8DALL/BLL are 512Mb Dual Die device containing two units of 256Mbit Pseudo Static Random Access Memory, organized as 64M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation, designed especially for Mobile and Automotive applications
Key Features 512-Mbit (64M × 8) HyperRAM™ PSRAM High-speed HyperBus interface Clock frequency up to 166 MHz Fast 36 ns access time Single-ended clock architecture with reduced pin count Operating voltage range: 2.7 V to 3.6 V Industrial temperature range: −40°C to +85°C Low-power volatile memory solution Surface-mount 24-TFBGA (6 mm × 8 mm) package Suitable for graphics, AI edge devices, networking, and embedded systems requiring large external memory capacity.

Properties

IS66WVH64M8DBLL-166B1LI

ISSI, Integrated Silicon Solution Inc

Integrated Circuits

IC

Rohs

parametric-v1

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