Pin Configuration Overview

Thought for 1 min 44 sec

Using the datasheet as the source of truth is the right way to build a part pin table, especially for exact pin numbers and shared configuration pins . For IC-style parts like this FPGA, pin types are typically classified as Power In, Ground, Input, Output, Bi-Directional, or Unspecified based on the datasheet function .

Here is a pin-by-pin table for ICE40UP5K-SG48I:

Pin table

Table

Pin #	Pin Name	Function	I/O characteristics	Special considerations
1	IOT_49b	Bank 0 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 0
2	IOT_51a	Bank 0 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 0
3	IOT_51b	Bank 0 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 0
4	RGB0	RGB LED driver / GPIO	Open-drain output or GPIO	Can be used as open-drain GPIO; when RGB enabled can sink up to 24 mA for LED drive
5	RGB1	RGB LED driver / GPIO	Open-drain output or GPIO	Same as RGB0
6	RGB2	RGB LED driver / GPIO	Open-drain output or GPIO	Same as RGB0
7	VCCIO_0	Bank 0 I/O supply	Power In	Sets Bank 0 I/O voltage standard
8	VCC	Core supply	Power In	Core power rail
9	IOT_41b	Bank 0 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 0
10	IOT_37a	GPIO / global input G1	Bi-directional GPIO, clock/global-capable input	Suitable for clocks or other high-fanout signals
11	IOT_37b	Bank 0 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 0
12	IOT_36b	Bank 0 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 0
13	IOT_36a_WAKEN	GPIO / wake-enable pin	Bi-directional GPIO / control input	Wake-capable pin; reserve if low-power wake is needed
14	IOT_33a_SPI_SO	Config SPI data out / GPIO	Output during configuration, GPIO after config	Shared with configuration SPI; do not repurpose at power-up
15	IOT_33b_SPI_SI	Config SPI data in / GPIO	Input during configuration, GPIO after config	Shared with configuration SPI; do not repurpose at power-up
16	IOT_34a_SPI_SCK	Config SPI clock / GPIO	Input or output during configuration, GPIO after config	Shared with configuration SPI; role depends on master/slave config mode
17	IOT_39a_SPI_SS_B	Config SPI chip select / GPIO	Input or output during configuration, GPIO after config	Shared with configuration SPI; not free for user logic until configuration completes
18	IOT_39b_G2	GPIO / global input G2	Bi-directional GPIO, clock/global-capable input	Good candidate for clock/high-fanout input
19	GND_LED	LED-driver ground	Ground	Tie to board ground; return path for RGB drivers
20	IOT_46b_G0	GPIO / global input G0	Bi-directional GPIO, clock/global-capable input	Good clock/global input pin
21	VPP_2V5	NVCM programming supply	Power In	Required for NVCM programming/operation; treat as dedicated supply pin
22	VCCPLL	PLL supply	Power In	Clean supply recommended; decouple carefully
23	IOT_44b	Bank 0 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 0
24	IOT_44a	Bank 0 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 0
25	IOB_3b_G6	Bank 2 GPIO / global input G6	Bi-directional GPIO, clock/global-capable input	Good candidate for clock/high-fanout signals
26	IOB_2a_G7	Bank 2 GPIO / global input G7	Bi-directional GPIO, clock/global-capable input	Good candidate for clock/high-fanout signals
27	IOB_8a	Bank 2 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 2
28	IOB_9b	Bank 2 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 2
29	VCCIO_2	Bank 2 I/O supply	Power In	Sets Bank 2 I/O voltage standard
30	VCC	Core supply	Power In	Core power rail
31	IOB_16a	Bank 1 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 1
32	IOB_16b	Bank 1 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 1
33	SPI_VCCIO1	Bank 1 / config I/O supply	Power In	Supplies Bank 1 and configuration SPI I/O levels
34	IOB_18a	Bank 1 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 1
35	IOB_18b_G3	Bank 1 GPIO / global input G3	Bi-directional GPIO, clock/global-capable input	Good candidate for clock/high-fanout signals
36	IOB_20a	Bank 1 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 1
37	IOB_20b_G4	GPIO / G4 / CDONE shared pin	Bi-directional GPIO, config status shared pin	Has weak pull-up to SPI_VCCIO1; used for configuration-done indication before becoming GPIO
38	IOB_24a	Bank 1 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 1
39	IOB_25b	Bank 1 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 1
40	IOB_29a	Bank 1 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 1
41	IOB_29b	Bank 1 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 1
42	IOB_31a	Bank 1 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 1
43	IOB_31b	Bank 1 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 1
44	IOB_35a_G5	Bank 1 GPIO / global input G5	Bi-directional GPIO, clock/global-capable input	Good candidate for clock/high-fanout signals
45	IOB_35b	GPIO / CRESET_B shared pin	Input during configuration, GPIO after config	Active-low configuration reset; no internal pull-up, so use external 10 kΩ pull-up to SPI_VCCIO1 if not actively driven
46	IOB_23b	Bank 1 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 1
47	IOB_6a	Bank 2 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 2
48	IOB_4a	Bank 2 general-purpose I/O	Bi-directional GPIO	Standard user I/O in Bank 2

Important usage notes

Table

Topic	Notes
User I/O count	SG48 package provides 39 user I/Os total
Bank supplies	Bank 0 uses VCCIO_0, Bank 1 uses SPI_VCCIO1, Bank 2 uses VCCIO_2
Configuration pins	SPI configuration pins and shared status/reset pins are not freely reusable at power-up; they only become normal GPIO after configuration completes
Default I/O state	Before configuration, I/Os are tri-stated with a weak pull-up to VCCIO
CDONE	Shared on pin 37; includes a weak pull-up to SPI_VCCIO1
CRESET_B	Shared on pin 45; active low, no internal pull-up
RGB pins	Pins 4-6 are special open-drain LED-capable outputs, not plain push-pull LED pins
PLL supply	VCCPLL should be kept clean and well-decoupled
LED ground	GND_LED should tie to board ground
Exposed pad	The SG48 exposed paddle must be connected to GND
Differential use	General sysIO supports single-ended standards and comparator-style differential usage; no dedicated true-LVDS pin class was identified in the extracted datasheet text

If you want, I can next turn this into:

a CSV-style pin list
a Flux terminal property table with recommended pin types/sections/groups
or a part-project patch plan to fix the current pin definitions in this project.

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Project Name

ICE40UP5K-SG48I

Description

iCE40 UltraPlus™ Field Programmable Gate Array (FPGA) IC 39 1171456 5280 48-VFQFN Exposed Pad #commonpartslibrary #integratedcircuit #ice40

Properties

Manufac… Number

ICE40UP5K-SG48I

Manufac…er Name

Texas Instruments Inc.

Designator Prefix

Part Type

Integrated Circuit

Datasheet URL

verical.com/datasheet/lattice-semiconductor-fpga-ICE40UP5K-SG48I-7354953.pdf

License

creativecommons.org/licenses/by/4.0/

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adrian95 / ICE40UP5K-SG48I

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