Review complete. The part already has a Datasheet URL set, so I did not overwrite it; I also found the official EPC datasheet at https://epc-co.com/epc/documents/datasheets/EPC2019_datasheet.pdf.
Key findings:
MPN/manufacturer match: EPC2019, Efficient Power Conversion / EPC.
Part type matches: enhancement-mode N-channel eGaN FET.
Pin count matches: 7 pads.
Symbol pin numbering matches datasheet:
1 = Gate
2, 4, 6 = Source
3, 5 = Drain
7 = Substrate
Footprint pad geometry and placement match the datasheet land pattern: 0.23 mm circular pads, 0.23 × 0.68 mm oval pads, 0.6 mm / 0.45 mm pitch relationships, ~2.766 × 0.950 mm die outline.
Mismatches / issues flagged:
Project description says RDS(on) 42 mΩ max, but the datasheet extraction reports 50 mΩ max at VGS = 5 V, ID = 7 A, with 36 mΩ typical. The web search snippet also reported 42 mΩ, so this should be verified visually in the official PDF revision you intend to use.
Project description says Qg ≈ 2.9 nC, while the datasheet extraction reports Qg typ 1.8 nC, max 2.5 nC.
Schematic terminal Pin Type fields are all Unspecified; they should ideally be set to Gate/Input, Drain/Power, Source/Power, and Substrate/Passive or Power depending on Flux conventions.
The part has no BOM item because this is a published part project made from terminal components, not a design using the part.
To get started, talk to Flux or create a New Document.
Reviews
Documents
Documents are markdown text files which describe project goals, capture details, or even simulation outputs.
Assets
kicad_mod
EPC2019
EPC2019.kicad_modFootprint
EPC2019-thumb.png
EPC2019-thumbThumbnail
EPC2019
EPC2019 Symbol.svgDefault
stp
EPC2019
EPC2019.stp3D Model
EPC2019
GANFET N-CH 200V 8.5A DIE
The EPC2019 is an enhancement-mode N-channel Gallium Nitride (eGaN®) power transistor designed for high-speed and high-efficiency power conversion applications. With a 200 V drain-to-source voltage rating, 42 mΩ maximum RDS(on), and 8.5 A continuous drain current, it offers significantly lower switching losses than conventional silicon MOSFETs. Its ultra-low gate charge, zero reverse recovery charge (QRR), and fast switching characteristics make it ideal for high-frequency switching circuits. The device is supplied in a bare die (passivated die with solder bars) package for optimized thermal and electrical performance in compact, high-density designs.
Key Features
Enhancement-mode N-channel eGaN® FET
200 V drain-to-source voltage (VDS)
42 mΩ maximum RDS(on) @ VGS = 5 V
8.5 A continuous drain current
Ultra-low gate charge (Qg ≈ 2.9 nC)
Zero reverse recovery charge (QRR) for reduced switching losses
Supports high-frequency switching operation
Gate drive compatible with 0 V OFF / 5 V ON (no negative gate voltage required)
Bare die package for compact, high-performance power designs
Operating junction temperature: −40°C to +150°C