Part Datasheet Review and Updates
Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.
Worked for 2 mins 23 sec
I reviewed the part against TI’s official DS90UB953-Q1 information; the Datasheet URL was already set, so I did not change it. The pin names/count mostly match, but I flagged property/metadata issues including EPAD typed as unspecified, RES1 typed as input, I²C pins typed as output, LPF pins unspecified, and missing richer part properties/descriptions. Full review is in DS90UB953TRHBRQ1 Part Datasheet Review.
Looking at the datasheet of this component, can you group together pins by their functions? for example for Power, VDD etc
NOTE: If you group them, can you not add the same pin if you already added them in a group? You should know which pin function is common for its function
Worked for 2 mins 30 sec
I grouped every DS90UB953-Q1 terminal into exactly one functional group: Power, Ground/Thermal, MIPI CSI-2 Input, FPD-Link III, I²C, GPIO, Clock, Control, Loop Filter, and Reserved. I also flagged current property fixes like
EPAD → Ground and I2C_SDA/SCL → Bi-Directional; full details are in DS90UB953-Q1 Pin Functional Groups.Fix pin metadata
Show wrong types
Symbol grouping plan
Check reserved pins
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Ask about this doc
DS90UB953-Q1 Pin Functional Groups
Source basis: TI DS90UB953-Q1 datasheet pinout as represented in this part project, plus the existing terminal names/pin numbers in the schematic. Each pin is assigned to exactly one functional group; no pin is repeated across groups.
Recommended Groups
Table
| Functional Group | Pins | Notes / Common Function |
|---|---|---|
| Power / Supply | 10 VDDPLL_CAP, 11 VDDPLL, 15 VDDDRV_CAP, 16 VDDDRV, 25 VDDD, 26 VDDD_CAP | Device supply and required supply bypass/capacitor pins. Keep all VDD/VDD*_CAP pins together as the power block. |
| Ground / Thermal | 33 EPAD | Exposed thermal pad / ground return. This should be treated as Ground, not Unspecified. |
| MIPI CSI-2 Input | 1 CSI_D1P, 2 CSI_D1N, 3 CSI_D0P, 4 CSI_D0N, 5 CSI_CLKP, 6 CSI_CLKN, 29 CSI_D3P, 30 CSI_D3N, 31 CSI_D2P, 32 CSI_D2N | CSI-2 differential data and clock inputs from the image sensor. I kept all CSI lanes in one group, including lanes 0–3 and CSI clock. |
| FPD-Link III Serial Link | 13 DOUT-, 14 DOUT+ | High-speed differential serializer output pair. |
| I²C Control Interface | 23 I2C_SDA, 24 I2C_SCL | Bidirectional open-drain control/configuration bus. These should be grouped together and generally typed as bidirectional/open-drain, not output-only. |
| GPIO / General Purpose I/O | 17 GPIO_0, 18 GPIO_1, 27 GPIO_2, 28 GPIO_3 | Bidirectional GPIO pins. |
| Clock / Synchronization | 19 CLK_OUT/IDX, 20 CLKIN | Reference clock input and clock/index output function. |
| Control / Configuration | 8 PDB, 21 MODE | Device power-down / enable and mode strap/configuration. |
| Loop Filter / PLL Passive | 9 LPF1, 12 LPF2 | PLL loop-filter related pins; keep separate from generic power because these are analog/passive filter connections, not supply inputs. |
| Reserved | 7 RES0, 22 RES1 | Reserved pins. Keep them in their own reserved group rather than control or GPIO. |
Suggested Flux Properties
For each terminal, set:
Table
| Pin | Section | Pin Group | Suggested Pin Type |
|---|---|---|---|
VDDPLL_CAP, VDDPLL, VDDDRV_CAP, VDDDRV, VDDD, VDDD_CAP | Power | Power | Power In |
EPAD | Ground | Ground | Ground |
CSI_DxP/N, CSI_CLKP/N | Communication | MIPI CSI-2 | Input |
DOUT+, DOUT- | Communication | FPD-Link III | Bi-Directional or Output* |
I2C_SDA, I2C_SCL | Communication | I2C | Bi-Directional |
GPIO_0–GPIO_3 | GPIO | GPIO | Bi-Directional |
CLKIN, CLK_OUT/IDX | Clock | Clock | CLKIN = Input; CLK_OUT/IDX = Bi-Directional or Output depending desired ERC behavior |
PDB, MODE | Control | Control | Input |
LPF1, LPF2 | Analog | Loop Filter | Passive or Unspecified |
RES0, RES1 | No Connect / Reserved | Reserved | Not Connected or Unspecified |
* For
DOUT+/-, the project currently uses Bi-Directional. If you want stricter ERC, Output may be more appropriate for the serializer-side high-speed link; keep Bi-Directional if modeling the FPD-Link channel as bidirectional due to back-channel behavior.Mismatches to Fix in Current Part
EPADis currently Unspecified; it should be Ground.I2C_SDAandI2C_SCLare currently Output; they should be Bi-Directional because I²C is bidirectional/open-drain.RES1is currently Input; it should be Reserved / Not Connected or Unspecified, depending how strictly you want ERC to enforce reserved-pin handling.LPF1andLPF2are currently Unspecified; that is acceptable if Flux has no better passive/analog filter terminal type, but I would group them as Loop Filter so they are not mixed with power.
No-Duplicate Assignment Check
All 33 terminals are accounted for exactly once:
1–6 MIPI CSI-2, 7 Reserved, 8 Control, 9 Loop Filter, 10–11 Power, 12 Loop Filter, 13–14 FPD-Link III, 15–16 Power, 17–18 GPIO, 19–20 Clock, 21 Control, 22 Reserved, 23–24 I²C, 25–26 Power, 27–28 GPIO, 29–32 MIPI CSI-2, 33 Ground/Thermal.
Recommended Groups
Suggested Flux Properties
Mismatches to Fix in Current Part
No-Duplicate Assignment Check
