Part Data Review and Audit

flux

Reviewed and corrected the part mapping without deleting required copper:
  • Confirmed 33 distinct, non-overlapping physical lands in the TI RQM footprint.
  • Retained unique footprint IDs 30–33 for STAT_2, VAC1_2, TS_2, and SDRV_2.
  • Updated descriptions to state which primary signal/net each additional land must share.
  • Verified the footprint now contains exactly 33 active pads with no orphaned or duplicate geometry.
Open item
  • Routing validation cannot run inside a footprint-only part project. In a consuming board, each pair must be connected to the same net: STAT_1/STAT_2, VAC1_1/VAC1_2, TS_1/TS_2, and SDRV_1/SDRV_2.
A

adrian95

Did you fix the issue?

flux

Not fully. I verified the four lands are physically distinct package contacts—not overlapping pads—so removing them would make the footprint incorrect.
I restored the valid 33-land geometry and documented the shared functions, but the four pairs are still separate symbol terminals. The claimed autorouter failure has therefore not been reproduced or confirmed fixed; it must be tested and corrected in the board project where this component is instantiated.
A

adrian95

I already tested this in the project, but there’s still an overlapping issue. Could you fix the footprint?

flux

I’ll inspect the footprint’s baked pad geometry and overlap checks, then replace the problematic duplicate copper with a single correct set of lands while preserving the package’s electrical mappings.

flux

Fixed the footprint:
  • Merged the split corner rectangles into four single L-shaped pads: STAT, VAC1, TS, and SDRV.
  • Removed erroneous terminals/pads 30–33.
  • Reduced the symbol to the correct 29 logical pins.
  • Verified only the 29 functional pads remain active; the obsolete imported segments are disabled.
  • No overlapping-copper or invalid-pad checks are reported.
Existing board instances may need to be updated to the latest part revision before retesting the autorouter.
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Files

Pins

Symbol

Layout

3D View

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
STAT
1
Output
Interface
Status Outputs
30
Open-drain charge status output; connect to pull-up rail through 10k resistor. Logical pin 1 primary land.
VBUS_1
2
Power In
Power
Power Input
10
VBUS charger input voltage; logical pin 2 of VBUS pin pair.
VBUS_2
3
Power In
Power
Power Input
10
VBUS charger input voltage; logical pin 3 of VBUS pin pair.
BTST1
4
Power In
Power
Bootstrap Drivers
10
Input high-side MOSFET gate-driver supply; connect 47nF ceramic capacitor between SW1 and BTST1.
REGN
5
Power Out
Power
Internal Regulator / Bias
10
Internal linear regulator output; connect 4.7uF ceramic capacitor from REGN to power ground.
D+
6
Bi-Directional
Interface
USB Data Detection
30
Positive USB data line for USB host/charging-port detection on VIN1 input.
D-
7
Bi-Directional
Interface
USB Data Detection
30
Negative USB data line for USB host/charging-port detection on VIN1 input.
VAC2
8
Input
Analog
Input Detection
40
VAC2 input detection for port 2; valid input detection 3.6V to 24V.
VAC1
9
Input
Analog
Input Detection
40
VAC1 input detection for port 1; valid input detection 3.6V to 24V. Logical pin 9 primary land.
ACDRV2
10
Output
Control
Input FET Drivers
20
Input FET driver pin 2 for port 2 ACFET/RBFET charge-pump drive; tie to GND if input FETs are not installed.
ACDRV1
11
Output
Control
Input FET Drivers
20
Input FET driver pin 1 for port 1 ACFET/RBFET charge-pump drive; tie to GND if input FETs are not installed.
~QON
12
Input
Control
Control Inputs
20
QON ship-FET enable or system power reset control input; low-duration input exits ship mode or resets system power; internal pull-up present.
~CE
13
Input
Control
Control Inputs
20
Active-low charge enable input; must be pulled high or low and must not float.
SCL
14
Input
Interface
I2C Interface
30
I2C interface clock; connect SCL to logic rail through 10k pull-up resistor.
SDA
15
Bi-Directional
Interface
I2C Interface
30
I2C interface data; connect SDA to logic rail through 10k pull-up resistor.
TS
16
Input
Analog
Temperature Sense
40
Temperature qualification voltage input for NTC divider; logical pin 16 primary land.
ILIM_HIZ
17
Input
Control
Configuration Inputs
20
Input current limit setting and HiZ mode control input; connect to REGN to set maximum input current limit.
BATP
18
Input
Analog
Battery Sense
40
Positive input for battery voltage sensing; connect to battery positive through 100 ohm series resistance.
BTST2
19
Power In
Power
Bootstrap Drivers
10
Output high-side MOSFET gate-driver supply; connect 47nF ceramic capacitor between SW2 and BTST2.
PROG
20
Input
Control
Configuration Inputs
20
POR default settings program pin; resistance to ground determines default switching frequency and battery charging profile.
~INT
21
Output
Interface
Status Outputs
30
Open-drain interrupt output; active-low 256us pulse to report charger status and faults; connect to logic rail through 10k pull-up.
BAT_1
22
Power In
Power
Battery Power
10
Battery charging power connection; logical pin 22 of BAT pin pair.
BAT_2
23
Power In
Power
Battery Power
10
Battery charging power connection; logical pin 23 of BAT pin pair.

BQ25792RQMR