I’ll research the manufacturer’s datasheet and distributor information, then create the application guide with verified specifications, practical wiring advice, and clearly labeled alternatives.
The datasheet confirms that the advertised on-resistance values are maximum ratings, not typical values, and that the 1.4 W dissipation rating uses a ≤10-second thermal condition. I’m making those distinctions explicit and flagging pinout and replacement-compatibility details that the available evidence could not fully verify.
The Alpha & Omega Semiconductor (AOS) AO3400A is a 30 V N-channel enhancement-mode trench MOSFET in a three-terminal SOT23 surface-mount package. Its principal application is a logic-controlled low-side load switch or PWM switch for small loads, with the allowable current determined by gate drive, loss, safe operating area, and PCB cooling—not the headline current rating alone. AOS product information.
Scope: this guide describes the AOS device, not similarly named devices from other manufacturers. Reviewed October 6, 2026. Numerical device specifications below have citation-backed datasheet evidence; suggested circuit values are engin...
Created the AO3400A Application and Usage Guide with all seven requested sections, source citations, practical wiring guidance, and two library-linked alternatives. It distinguishes typical from maximum on-resistance and explains the thermal limitations behind the 1.4 W rating.
Open verification items: pin numbering, package pitch, and full drop-in compatibility are explicitly flagged; confirm these before using the guide for PCB release or component substitution.
The Alpha & Omega Semiconductor (AOS) AO3400A is a 30 V N-channel enhancement-mode trench MOSFET in a three-terminal SOT23 surface-mount package. Its principal application is a logic-controlled low-side load switch or PWM switch for small loads, with the allowable current determined by gate drive, loss, safe operating area, and PCB cooling—not the headline current rating alone. AOS product information.
Scope: this guide describes the AOS device, not similarly named devices from other manufacturers. Reviewed October 6, 2026. Numerical device specifications below have citation-backed datasheet evidence; suggested circuit values are engineering starting points, not manufacturer-mandated values. Pin numbering, package pitch, and complete substitution qualification remain explicitly unresolved where noted.
1. Quick Specifications
Absolute maximum ratings — stress limits, not operating targets
Table
Parameter
Absolute maximum
Conditions / interpretation
Drain-source voltage, VDS
30 V
Include supply tolerance and switching overshoot; do not operate at the limit.
Gate-source voltage, VGS
±12 V
Relative to the source, not circuit ground. A nominal 12 V driver leaves no transient margin.
Continuous drain current, ID
5.7 A at TA = 25°C; 4.7 A at TA = 70°C
Headline product summary uses VGS = 10 V. Actual permissible current depends on thermal conditions and SOA.
Pulsed drain current, IDM
30 A
Pulse-limited rating; not a permissible continuous current.
Power dissipation, PD
1.4 W at TA = 25°C; 0.9 W at TA = 70°C
Note B uses ≤10 s junction-to-ambient thermal resistance; not a typical continuous dissipation capability.
Junction and storage temperature
−55°C to +150°C
This is not an assurance of full rated current at +150°C ambient.
Absolute-rating evidence:
Electrical characteristics and practical operating guidance
Table
Parameter
Verified value
Conditions / practical use
RDS(on), 10 V gate drive
18 mΩ typical; 26.5 mΩ maximum
ID = 5.7 A, TJ = 25°C.
RDS(on), 4.5 V gate drive
19 mΩ typical; 32 mΩ maximum
ID = 5 A, TJ = 25°C.
RDS(on), 2.5 V gate drive
24 mΩ typical; 48 mΩ maximum
ID = 3 A, TJ = 25°C.
RDS(on), elevated junction temperature
28 mΩ typical; 38 mΩ maximum
VGS = 10 V, ID = 5.7 A, TJ = 125°C; do not apply this maximum to 2.5 V drive.
Gate threshold, VGS(th)
0.65 V minimum; 1.05 V typical; 1.45 V maximum
VDS = VGS, ID = 250 µA. Threshold is not the voltage for full enhancement.
Total gate charge, Qg
6 nC typical; 7 nC maximum
Gate-charge test entry: VGS = 4.5 V, VDS = 15 V, ID = 5.7 A.
Steady-state RθJA
100°C/W typical; 125°C/W maximum
Datasheet reference PCB only; not a prediction for your layout.
Package
SOT23, three terminals
Use the manufacturer's package drawing to qualify the land pattern.
Lead pitch
Unverified for the AOS package in this research
Do not substitute a nominal generic SOT23 pitch for a verified AOS drawing.
Practical logic drive
3.3 V or 5 V low-side control can be suitable
Engineering guidance: ensure actual GPIO VOH minus source rise stays above the gate voltage needed for the chosen resistance bound. No guaranteed 3.3 V RDS(on) point was extracted; use the 2.5 V bound conservatively only after checking current and temperature applicability.
The reference thermal measurement uses a 1 in² FR-4 board with 2 oz copper in still air at TA = 25°C, and the datasheet explicitly states that the application value depends on the user's board. Its 1.4 W rating uses ≤10 s thermal resistance.
Recommended operating conditions: this research did not establish a separate manufacturer recommended-operating-conditions table. Select supply voltage, current, temperature, and gate drive with margin below absolute limits; the suggestions here are not an additional manufacturer guarantee.
2. Pinout & Connections
Verification limitation: the expected numerical assignment below is 1 = gate, 2 = source, 3 = drain, but the AOS pinout drawing could not be validated from the extracted evidence after two attempts. Treat the pin-number column as provisional and confirm the original manufacturer's top-view drawing before creating a symbol, routing a board, or approving assembly. Do not use another manufacturer's AO3400A datasheet as proof for AOS.
Table
Pin Number
Pin Name
Description
Best Practice
1 — provisional
G, Gate
Controls channel conduction according to VGS.
Drive through a selected series resistor; add a gate-to-source pull-down. A 10 kΩ pull-down is a practical starting point, not an AO3400A datasheet requirement.
2 — provisional
S, Source
Gate-drive reference and low-side power return.
Tie to power GND for the standard low-side circuit; reference controller/driver ground locally to this node without sharing a long high-current return.
3 — provisional
D, Drain
Connects to the load's switched negative terminal.
Connect load positive to the supply; keep drain overshoot below the 30 V stress limit with margin. Add external inductive-load suppression when needed.
AO3400A low-side MOSFET switch for 3.3 V or 5 V control
After confirming pin numbers, wire by terminal function:
Connect the source to power GND and the load between +VLOAD and drain. Connect controller ground to the same source-reference system. Logic HIGH turns the load on; logic LOW turns it off. This topology switches the load's ground connection, so it is unsuitable for loads that must retain an uninterrupted ground reference. TI low-side switch guidance.
Fit a 10 kΩ gate-to-source pull-down at the MOSFET as an engineering starting point. It holds the gate near the source when the MCU output is high impedance; select a stronger pull-down or an active driver if measured startup or drain dV/dt can induce turn-on. TI gate-drive fundamentals.
Place a series gate resistor near the gate. For a GPIO-controlled, relatively slow switch, 330 Ω is an illustrative initial value: idealized initial current is 3.3 V / 330 Ω = 10 mA or 5 V / 330 Ω = 15.2 mA, before GPIO output resistance and MOSFET internal resistance. Verify these pulses against the MCU specification; this is not a universal safe resistor or a high-frequency PWM recommendation. Tune from measured VGS/VDS ringing and switching loss; use a gate driver when the GPIO cannot charge and discharge the gate fast enough. TI external gate resistor selection.
For a relay, solenoid, or other applicable inductive load, add a flyback diode across the load: cathode to +VLOAD, anode to drain. Select its reverse-voltage, peak/average current, recovery behavior, and energy/thermal capability for the actual load and PWM operation. The MOSFET body diode does not provide this drain-to-positive-supply recirculation path. A simple diode slows current decay; use a properly engineered higher-voltage clamp when fast release is required. Inductive turn-off energy must be safely clamped; see TI inductive-load guidance.
The MOSFET has no supply pin and therefore no mandatory supply bypass capacitor of its own. Add ceramic decoupling and bulk capacitance across +VLOAD and power GND as required by the load current step and interconnect impedance; place it close to the switching-current loop. Size effective capacitance using C ≥ I × Δt / ΔV as a first-order charge-balance calculation, then account for capacitor ESR, bias derating, ripple, and rail overshoot. Do not arbitrarily prescribe 1 µF as sufficient for every motor or relay.
Gate-drive selection: do not use VGS(th) as the turn-on voltage. At the threshold test point, drain current is only 250 µA. The datasheet provides resistance limits at 2.5 V, 4.5 V, and 10 V, with different test currents.
Thermal sizing example — calculated, not measured: at 3 A continuous and the 25°C, 2.5 V maximum resistance of 48 mΩ, conduction loss is P = I²R = 3² × 0.048 = 0.432 W. Using the reference-board maximum steady-state RθJA of 125°C/W gives an initial rise of 54°C; this underestimates operating loss if resistance rises with junction temperature, and excludes switching loss. Iterate with temperature-dependent resistance and the actual PCB thermal behavior; do not present this example as a guaranteed 3 A capability.
For PWM, estimate conduction loss with RMS channel current and add switching loss from the actual overlap of VDS and ID. Datasheet switching times measured with a specified laboratory driver are not the switching times of an MCU plus series resistor.
LED series-resistor and USB-C CC-pin calculations are not intrinsic requirements of this MOSFET and are intentionally omitted; a connected bare LED still needs its own independently designed current limiter.
4. PCB Layout & Routing Guidelines
Heat spreading and thermal relief: provide useful drain copper and a low-resistance source return. Avoid narrow thermal-relief spokes that undermine the required current and heat flow; coordinate solid or suitably wide connections with assembly needs. The reference thermal data assumes 1 in² FR-4 with 2 oz copper, and actual performance is layout-dependent.
High-current paths: use short, wide drain/source copper or pours, and check pads, neckdowns, vias, and connectors as well as long traces. Determine width from copper thickness, current waveform, permitted temperature rise, and voltage-drop budget; no single universal width follows from “5.7 A.” Validate the finished board thermally at maximum ambient.
Gate loop and source reference: place the gate resistor and pull-down adjacent to the MOSFET, keep the gate loop short, and route the driver reference to the source without a shared high-current path where practical. Keep noisy drain copper away from the gate. TI external gate resistor selection and loop-inductance guidance.
Inductive-load and bypass placement: minimize the recirculation loop between load, flyback diode, and drain; minimize the supply-capacitor/power-switch loop. Keep high-current switching returns away from controller ground. Component values and locations must reflect where the actual load and cable inductance reside.
Package and unrelated interfaces: verify the AOS package drawing, pin-1 orientation, solder-mask clearances, and land pattern before release; package pitch was not verified here. The MOSFET does not require differential-pair routing; any nearby high-speed differential interfaces have their own constraints and should be kept away from the switching node.
5. Common Pitfalls / Things to Watch Out For
Treating 5.7 A and 1.4 W as unconditional continuous capability. The power rating uses a ≤10 s thermal condition on a defined reference PCB. Calculate conduction and switching losses with gate-voltage and temperature dependence, check SOA for startup/inrush or linear operation, and measure temperature on the actual board. The project description's 26.5/32/48 mΩ figures are maximum values, not typical values.
Assuming a low threshold makes every GPIO connection safe. A floating gate, inadequate VOH, source bounce, or slow transitions can cause partial conduction and overheating. Use a gate-to-source pull-down, verify actual VGS at the device, select the series resistor/driver for the required edge rate, and add inductive-load suppression. Never drive this ±12 V gate directly from an unqualified nominal 12 V power rail. TI common MOSFET mistakes.
6. Popular Alternatives & Equivalents
These are alternatives from different manufacturers, not blanket electrically identical drop-in replacements. Both were found in the Flux library. No unconditional drop-in replacement was verified: the original AOS numerical pin mapping and mechanical pitch remain unresolved, and the Nexperia datasheet extraction remained pending after retry. Check the original package drawings, terminal assignment, solder lands, gate charge, gate-voltage resistance limits, SOA, and thermal behavior before substitution.
Functionally similar; SOT23 package candidate. Pin- and footprint-compatibility not fully verified.
Manufacturer evidence identifies a G/S/D SOT23 top-view diagram but did not establish numeric pin assignment in the extracted record. RDS(on) maximum is 25 mΩ at 10 V/4 A, 28 mΩ at 4.5 V/3.5 A, and 68 mΩ at 2.5 V/2.5 A. The 2.5 V limit is worse than AO3400A's 48 mΩ; re-evaluate losses rather than comparing only 10 V ratings.
Nexperia's product page identifies PMV20EN as a 30 V N-channel trench MOSFET for low-side load switching. Nexperia's chemical-content page associates orderable PMV20ENR with PMV20EN in SOT23. Exact gate-voltage resistance limits and numerical pin mapping remain unverified in citation-backed extraction; no such numeric comparison is asserted here. Product page; orderable-part identification.
Library presence confirms availability of a library entry, not present distributor stock or correctness of its symbol/footprint.
7. Sourcing & Purchasing Guide
Table
Attribute
Details
Primary Distributors
Verified AOS listings: DigiKey, Arrow, and LCSC C20917. Distributor authorization was not independently audited in this research; prefer a currently AOS-franchised distributor and confirm through AOS when required.
Packaging Options
DigiKey lists Tape & Reel, Cut Tape, and Digi-Reel; Arrow lists tape-and-reel supply with small-quantity purchasing options. Confirm tape orientation and feeder requirements with the assembler.
Standard MOQ
DigiKey listing: 1 unit for Cut Tape; 3,000 units for a full reel; manufacturer standard package 3,000. These are listing-specific purchasing quantities, not a universal MOQ for all sellers.
Sourcing Advice
Specify Alpha & Omega Semiconductor AO3400A, not just “AO3400A.” The same marking/part-number string is used in listings from other manufacturers with different specifications. Avoid untraceable marketplace stock and retain manufacturer, lot/date-code, and invoice traceability. Confirm package, reel quantity, and all ordering suffixes against the actual supplier/manufacturer record; distributor packaging codes are not automatically manufacturer MPN suffixes. Stock, lead time, and price change; obtain a current quote before purchase.
The AOS product page currently lists Full Production; this guide does not treat third-party aggregator lifecycle labels as authoritative. AOS product information.
Sources
AOS manufacturer datasheet URL:AO3400A PDF. This source link identifies the document; the inline evidence citations above support individual specifications.
Alpha & Omega Semiconductor, AO3400A datasheet, Rev. 3.1, July 2023; revision verified from the document footer. Access the manufacturer's datasheet and separate package/tape-and-reel documents through the AOS AO3400A product page. The page's datasheet posting date, October 23, 2023, is not the PDF revision date.
Texas Instruments, Avoid Common Mistakes When Selecting and Designing With Power MOSFETs, SLPA021, especially sections 4–6: manufacturer application note. Revision/date not independently extracted here.
Texas Instruments, Fundamentals of MOSFET and IGBT Gate Driver Circuits, SLUA618A, Rev. A: manufacturer application note. Publication date not independently extracted here.
Texas Instruments, External Gate Resistor Selection Guide, SLLA385A, Rev. A: manufacturer technical note. Publication date not independently extracted here.
Texas Instruments, How To Drive Resistive, Inductive, Capacitive, and Lighting Loads, SLVAE30E, Rev. E: manufacturer application note. Used for general inductive-clamping principles, not as an AO3400A-specific reference design.
Diodes Incorporated, DMN3023L datasheet: manufacturer source; numerical resistance and functional package evidence extracted and cited above. Current PDF revision/date not verified here.
Nexperia, PMV20EN: manufacturer product page and PMV20ENR orderable-part record. Datasheet indexing did not complete after retry; citation-backed pin/resistance extraction remains unresolved. The searched document identifies version 2, July 5, 2018, but that revision identification is not independently validated by the datasheet evidence service.
DigiKey, Arrow, and LCSC product listings, linked in section 7, used as primary sources for their own catalog offerings and purchasing quantities, not to override manufacturer electrical specifications. Reviewed October 6, 2026.
1. Quick Specifications
Absolute maximum ratings — stress limits, not operating targets
Electrical characteristics and practical operating guidance
2. Pinout & Connections
3. Standard Application Circuit
AO3400A low-side MOSFET switch for 3.3 V or 5 V control