Reviewed ADC09SJ1300AAVT against TI’s official datasheet: https://www.ti.com/lit/ds/symlink/adc09sj1300.pdf. I recorded the URL in the project Implementation Details because this part project exposes the device as 144 terminal pins rather than a single editable IC component with a Datasheet URL property.

Key specs confirmed: Texas Instruments ADC09SJ1300AAVT, single-channel 9-bit 1.3-GSPS ADC, JESD204B/C interface, AAV 144-ball FCCSP/FCBGA, 10 mm × 10 mm, -40 to 85 °C, up to 17.16 Gbps SerDes, 1–4 lanes, ~940 mW single-channel power.

Cross-check result: the 144 schematic terminals and ball numbers match the TI AAV single-channel pinout, and the footprint matches a 12 × 12, 0.8 mm pitch, 10 mm × 10 mm BGA/FCCSP package. Main mismatch/cleanup item: all schematic terminal Pin Type fields are currently Unspecified, and detailed Pin Description properties are missing; functionally the names/ball map look correct, but the metadata is incomplete for ERC/documentation quality.

I’ll update the 144 terminal pins in batches with datasheet-derived Pin Type, Pin Description, and Section metadata, then spot-check the result.

First batch is updated; I’m normalizing the remaining pins to Flux’s standard Pin Type and Section values while keeping the datasheet descriptions specific.

Updated the ADC09SJ1300AAVT terminal metadata from the TI datasheet: all 144 pins now have Pin Type, Pin Description, and Section populated.

I also normalized the values to Flux-standard metadata where possible: supplies are Power In, grounds are Ground, DNC balls are Not Connected, JESD lanes are Data, SPI/SYNC are Interface, clocks/SYSREF/PLL outputs are Clock, analog pins are Analog, and control/status pins are Control.

Spot-check passed for representative pins: INA+, VD11_10, D0+, DNC_8, SYSREF+, TDIODE+, ~SCS, and AGND_1.