Part Data Review and Datasheet Update

adrian95

adrian95

Fix the missing Pin Type, Pin Description and section metadata from the datasheet.

flux

I’ll update the 144 terminal pins in batches with datasheet-derived Pin Type, Pin Description, and Section metadata, then spot-check the result.

flux

First batch is updated; I’m normalizing the remaining pins to Flux’s standard Pin Type and Section values while keeping the datasheet descriptions specific.

flux

Updated the ADC09SJ1300AAVT terminal metadata from the TI datasheet: all 144 pins now have Pin Type, Pin Description, and Section populated.
I also normalized the values to Flux-standard metadata where possible: supplies are Power In, grounds are Ground, DNC balls are Not Connected, JESD lanes are Data, SPI/SYNC are Interface, clocks/SYSREF/PLL outputs are Clock, analog pins are Analog, and control/status pins are Control.
Spot-check passed for representative pins: INA+, VD11_10, D0+, DNC_8, SYSREF+, TDIODE+, ~SCS, and AGND_1.
Run metadata review
Create pinout report
Check footprint pads
Add sourcing fields
Prepare export check
Sign up to send

To get started, talk to Flux or create a New Document.

Documents

    Documents are markdown text files which describe project goals, capture details, or even simulation outputs.

    Assets

    ADC09SJ1300AAVT-thumb.png

    ADC09SJ1300AAVT-thumb.png

    ADC09SJ1300AAVT-thumbThumbnail
    stp

    ADC09SJ1300AAVT

    ADC09SJ1300AAVT.stp3D Model
    ADC09SJ1300AAVT

    ADC09SJ1300AAVT

    ADC09SJ1300AAVT Symbol.svgDefault
    kicad_mod

    ADC09SJ1300AAVT

    BGA144C80P12X12_1000X1000X194.kicad_modFootprint

    ADC09SJ1300AAVT

    ADC09SJ1300AAVT thumbnail
    Analog to Digital Converters - ADC Single-channel, 9-bit, 1.3-GSPS analog-to-digital converter (ADC) with JESD204C interface 144-FCBGA -40 to 85
    ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltagecontrolled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
    Features • ADC Core: – Resolution: 9 Bit – Maximum sampling rate: 1.3GSPS – Non-interleaved architecture – Internal dither reduces high-order harmonics • Performance specifications (–1dBFS): – SNR (100 MHz): 53.5dBFS – ENOB (100 MHz): 8.5 Bits – SFDR (100 MHz): 64dBc – Noise floor (–20dBFS): –143dBFS • Full-scale input voltage: 80 mVPP-DIFF • Full-power input bandwidth: 6GHz • JESD204C Serial data interface: – Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes – Maximum baud-rate: 17.16Gbps – 64B/66B and 8B/10B encoding modes – Subclass-1 support for deterministic latency – Compatible with JESD204B receivers • Optional internal sampling clock generation – Internal PLL and VCO (7.2–8.2GHz) • SYSREF Windowing eases synchronization • Four clock outputs simplify system clocking – Reference clocks for FPGA or adjacent ADC – Reference clock for SerDes transceivers • Timestamp input and output for pulsed systems • Power consumption (1GSPS): – Quad Channel: 450mW / channel – Dual channel: 625mW / channel – Single channel: 940mW • Power supplies: 1.1V, 1.9V
    #CommonPartsLibrary #IntegratedCircuit #ADC #HighSpeedADC #RFADC #JESD204C #13GSPS #9bitADC #DirectRFSampling #TexasInstruments #MixedSignal #DataAcquisition #JESD204

    Properties

    Official datasheet: https://www.ti.com/lit/ds/symlink/adc09sj1300.pdf

    ADC09SJ1300AAVT

    Texas Instruments

    Integrated Circuits

    ti.com/lit/gpn/adc09sj1300

    IC

    TO

    parametric-v1

    creativecommons.org/licenses/by/4.0/

    Pricing & Availability

    See prices from popular manufacturers for your project.

    Controls