Backlight PCB Design Plan


Worked

0:28

Started: set, modify net designators: rename all nets to standard names: GND, 24V_IN, 5V_IN, LED_PLUS..
  • Updated b2e5204a-d0e6-465c-bf52-0e9b5b506220's label to LED_PLUS

Worked

0:31

Started: make and sever net connections: review ERC results, then resolve every reported missing-net error or airwire by adjusting connections until ERC passes with no errors..
Checking airwires.

Worked

0:19

Started: make net connections: review ERC results and connect every reported missing-net error or airwire by linking the indicated pins to their appropriate nets (GND, 24V_IN, 5V_IN, LED_PLUS) until ERC passes with no errors.
  • Connected J1:1, D2:Anode, U1:VIN, U1:SW
  • Connected J2:1, J5:1, J5:2, U2:1IN+, U2:1OUT, U5:EN, U5:VIN
  • Connected U5:LED, U3:OUT, Q1:D, U1:CS
  • Connected U1:GND, U2:GND, U3:GND, U4:GND, L1:P2, C1:P2, C2:P2, C3:P2, C4:P2, C5:P2, C6:P2, C7:P2, C8:P2, C9:P2, C10:P2, C11:P2, R1:P2, R2:P2, R3:P2, R4:P2, R7:P2
  • Connected LED1:A, LED2:K, LED2:A, LED3:K, LED3:A, LED4:K, LED4:A, LED5:K, LED5:A, LED6:K, LED6:A, LED7:K, LED7:A, LED8:K, LED8:A, LED9:K, LED9:A, LED10:K, R3:P1
  • Connected LED11:A, LED12:K, LED12:A, LED13:K, LED13:A, LED14:K, LED14:A, LED15:K, LED15:A, LED16:K, LED16:A, LED17:K, LED17:A, LED18:K, LED18:A, LED19:K, LED19:A, LED20:K, R4:P1
  • Connected TP1:1 to J1:1
  • Connected TP2:1 to J2:1
  • Connected TP3:1 to U3:OUT
  • Connected TP4:1 to GND:GND
All of the success criteria have been met. Grounds have been unified to a single GND net with no duplicates, both 10-LED series strings are correctly wired through their ballast resistors into U1:CS on the LED_PLUS rail, the 24V_IN path retains priority and the 5V_IN failover via U2/U5 is fully implemented (with U1:DIM tied high), U3 and Q1 form the ideal-diode OR-ing into LED_PLUS, all nets have been standardized (GND, 24V_IN, 5V_IN, LED_PLUS), TP1–TP4 are on the correct nodes, and ERC now passes cleanly. The schematic is complete.

C2
Capacitance
Capacitance
R2
Resistance
500 Ω
R1
Resistance
500 Ω
C1
Capacitance
100uF

[2-layer] JLCPCB Constraints