Backlight PCB Design Plan

Updated 12 nets

0:32

Connected J1:1, D2:Anode, U1:VIN, U1:SW

Connected J2:P1, J5:P1, J5:P2, U2:1IN+, U2:1OUT, U5:EN, U5:VIN, J2:P2

Connected U5:LED, U3:OUT, Q1:D, U1:CS

Connected GND:GND, U1:GND, U2:GND, U3:GND, U4:GND, L1:P2, C1:P2, C2:P2, C3:P2, C4:P2, C5:P2, C6:P2, C7:P2, C8:P2, C9:P2, C10:P2, C11:P2, R1:P2, R2:P2, R3:P2, R4:P2, R7:P2

Connected LED1:A, LED2:K, LED2:A, LED3:K, LED3:A, LED4:K, LED4:A, LED5:K, LED5:A, LED6:K, LED6:A, LED7:K, LED7:A, LED8:K, LED8:A, LED9:K, LED9:A, LED10:K

Connected LED11:A, LED12:K, LED12:A, LED13:K, LED13:A, LED14:K, LED14:A, LED15:K, LED15:A, LED16:K, LED16:A, LED17:K, LED17:A, LED18:K, LED18:A, LED19:K, LED19:A, LED20:K

Connected LED10:A to R3:P1

Connected LED20:A to R4:P1

Connected TP1:P1 to J1:1

Connected TP2:P1 to J2:P1

Connected TP3:P1 to U3:OUT

Connected TP4:P1 to GND:GND

Worked

0:17

Started: make net connections: connect U3 IN to 24V_IN, U3 OUT to LED_PLUS, Q1 Gate to U3 GATE, and Q1 Drain/Source appropriately on the LED_PLUS net..

Updated 3 nets

0:04

Connected U3:IN to J1:1

Connected U3:OUT, Q1:D, Q1:S

Connected U3:GATE to Q1:G

Worked

0:28

Started: set, modify net designators: rename all nets to standard names: GND, 24V_IN, 5V_IN, LED_PLUS..

Updated labels for 1 net label

0:04

Updated b2e5204a-d0e6-465c-bf52-0e9b5b506220's label to LED_PLUS

Worked

0:31

Started: make and sever net connections: review ERC results, then resolve every reported missing-net error or airwire by adjusting connections until ERC passes with no errors..
Running Airwires check.

Worked

0:19

Started: make net connections: review ERC results and connect every reported missing-net error or airwire by linking the indicated pins to their appropriate nets (GND, 24V_IN, 5V_IN, LED_PLUS) until ERC passes with no errors.

Updated 10 nets

0:17

Connected J1:1, D2:Anode, U1:VIN, U1:SW

Connected J2:1, J5:1, J5:2, U2:1IN+, U2:1OUT, U5:EN, U5:VIN

Connected U5:LED, U3:OUT, Q1:D, U1:CS

Connected U1:GND, U2:GND, U3:GND, U4:GND, L1:P2, C1:P2, C2:P2, C3:P2, C4:P2, C5:P2, C6:P2, C7:P2, C8:P2, C9:P2, C10:P2, C11:P2, R1:P2, R2:P2, R3:P2, R4:P2, R7:P2

Connected LED1:A, LED2:K, LED2:A, LED3:K, LED3:A, LED4:K, LED4:A, LED5:K, LED5:A, LED6:K, LED6:A, LED7:K, LED7:A, LED8:K, LED8:A, LED9:K, LED9:A, LED10:K, R3:P1

Connected LED11:A, LED12:K, LED12:A, LED13:K, LED13:A, LED14:K, LED14:A, LED15:K, LED15:A, LED16:K, LED16:A, LED17:K, LED17:A, LED18:K, LED18:A, LED19:K, LED19:A, LED20:K, R4:P1

Connected TP1:1 to J1:1

Connected TP2:1 to J2:1

Connected TP3:1 to U3:OUT

Connected TP4:1 to GND:GND

flux

All of the success criteria have been met. Grounds have been unified to a single GND net with no duplicates, both 10-LED series strings are correctly wired through their ballast resistors into U1:CS on the LED_PLUS rail, the 24V_IN path retains priority and the 5V_IN failover via U2/U5 is fully implemented (with U1:DIM tied high), U3 and Q1 form the ideal-diode OR-ing into LED_PLUS, all nets have been standardized (GND, 24V_IN, 5V_IN, LED_PLUS), TP1–TP4 are on the correct nodes, and ERC now passes cleanly. The schematic is complete.
J3
J4 P1 - TP2 P1
Q1 D - U1 VIN
LED4 A - LED5 K
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
LED13 A - LED14 K
Q1 D - U1 VIN
Q1 D - U1 VIN
D2 A - C6 P1
Q1 D - U1 VIN
LED2 A - LED3 K
Q1 D - U1 VIN
J4 P1 - TP2 P1
Q1 D - U1 VIN
Q1 D - U1 VIN
LED4 A - LED5 K
U3 GATE - Q1 G
Q1 D - U1 VIN
LED8 A - LED9 K
Q1 D - U1 VIN
Q1 D - U1 VIN
LED13 A - LED14 K
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
LED4 A - LED5 K
LED13 A - LED14 K
LED4 A - LED5 K
U1 CS - R3 P1
Q1 D - U1 VIN
C4 P1 - R2 P2
LED8 A - LED9 K
U1 CS - R3 P1
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
LED13 A - LED14 K
Q1 D - U1 VIN
LED4 A - LED5 K
Q1 D - U1 VIN
LED7 A - LED8 K
Q1 D - U1 VIN
C10 P2 - GND GND
Q1 D - U1 VIN
LED13 A - LED14 K
Q1 D - U1 VIN
LED13 A - LED14 K
C10 P2 - GND GND
Q1 D - U1 VIN
Q1 D - U1 VIN
U3 GATE - Q1 G
Q1 D - U1 VIN
D2 A - C6 P1
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
LED13 A - LED14 K
Q1 D - U1 VIN
LED4 A - LED5 K
LED2 A - LED3 K
Q1 D - U1 VIN
LED17 A - LED18 K
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
LED18 A - LED19 K
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
LED4 A - LED5 K
Q1 D - U1 VIN
Q1 D - U1 VIN
LED4 A - LED5 K
Q1 D - U1 VIN
Q1 D - U1 VIN
LED17 A - LED18 K
J4 P1 - TP2 P1
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
LED18 A - LED19 K
LED13 A - LED14 K
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
C4 P1 - R2 P2
LED7 A - LED8 K
LED13 A - LED14 K
LED13 A - LED14 K
Q1 D - U1 VIN
Q1 D - U1 VIN
Q1 D - U1 VIN
J1
GND
LED12
TP2
GND
C2
Capacitance
Capacitance
LED14
GND
LED11
GND
GND
C11
Capacitance
Capacitance
LED10
GND
LED15
GND
LED20
GND
C3
Capacitance
Capacitance
LED6
TP3
C7
Capacitance
Capacitance
GND
LED18
LED3
GND
GND
GND
C4
Capacitance
Capacitance
LED13
LED2
LED17
LED4
LED7
C8
Capacitance
Capacitance
GND
LED9
LED5
C1
Capacitance
100uF
LED1
C10
Capacitance
Capacitance
GND
GND
C9
Capacitance
Capacitance
LED19
J1
GND
GND
C6
Capacitance
Capacitance
TP4
LED16
C5
Capacitance
Capacitance
GND
LED8
TP1
D3
D2
R2
Resistance
500 Ω
U3
J2
U2
U4
J5
R1
Resistance
500 Ω
D1
R3
Resistance
500 Ω
U1
Q1
L1
Inductance
1uH
R7
Resistance
500 Ω
R4
Resistance
500 Ω
J4

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    2-layer-thumbThumbnail

    [2-layer] JLCPCB Constraints

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    Dual-Input 5×4 Red LED Backlight Matrix PCB

    Properties

    Diagram
    


  
    
  
  
    
  



ORing










24 V rail

String 1

String 2

Boost path

Main path

5 V rail

Sense











24 V Input
U1: LED Driver
10 LEDs
10 LEDs
5 V Boost Driver
LED+ Node
5 V IN
U2: Comparator
J1
U3: Ideal Diode
Q1: MOSFET OR-ing

    U5: LT3465AES6#TRMPBF, Quantity: 1; R5: Generic Resistor, Quantity: 1; R6: Generic Resistor, Quantity: 1

    60 × 60

    mm

    LCSC

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    Controls