USB C Sensor Node
Worked for 1 min 56 sec
Built the schematic for a USB-C powered Wi‑Fi/BLE temperature + humidity sensor node using ESP32‑C3‑MINI‑1‑N4, SHT40, TPS25940 eFuse protection, MP28301 3.3 V buck regulation, USB-C CC pull-downs, USB data ESD, VBUS TVS, reset/boot controls, status LED, and test pads. I also created the key project files: Project Specification, Power Budget and Design Notes, Firmware Starter, Board Bring-Up Plan, and Technical Construction File.
Open items:
- I’m blocked from continuing because your account currently has no available ACUs, so AI tools are unavailable.
- Full check results show expected PCB airwires because layout/routing has not been done yet.
- Several generic passives/testpoints still need final manufacturer part numbers before manufacturing export.
- Layout still needs antenna keepout, SHT40 thermal isolation, USB-C ESD placement, and buck-regulator power-loop placement.
Suggested next steps:
- Refill/enable ACUs, then ask me to finish verification and clean remaining manufacturing metadata.
- Proceed to PCB placement with ESP32 antenna edge keepout and isolated SHT40 placement.
- Route the board, then run DRC/ERC again.
- Lock exact passive/inductor MPNs and generate manufacturing files.
Verify, layout, export
Finish verification
Place components
Route and review
Lock MPNs
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Board Bring-Up Plan — USB-C WiFi T-RH Sensor Node
Prerequisites
- Equipment: multimeter, current-limited USB 5 V supply or bench supply, oscilloscope if available, USB-C cable, PlatformIO host.
- Firmware: use
Firmware Starterafter assembly. - Safety: start with a 5 V current limit of 100–200 mA before full-power testing. Do not exceed 5 V until eFuse thresholds are verified.
1. Visual Inspection
- Inspect J1 USB-C pins and shield tabs for bridges.
- Confirm D1/D2 orientation and placement near J1.
- Confirm U3 TPS25940, U4 MP28301, U1 ESP32-C3 module, U2 SHT40, LED1 polarity.
- Confirm SHT40 area is clean; avoid flux residue and contamination.
2. Power Rail Verification
Table
| Rail | Source | Expected Voltage | Tolerance | Measure At | Current Limit | Pass Criteria |
|---|---|---|---|---|---|---|
| VBUS_RAW | J1 USB-C VBUS | 5.0 V | USB source tolerance | J1 VBUS / D1 pin 1 | 100–200 mA first power | Present when USB-C source attached. |
| 5V_PROT | U3 TPS25940 OUT | ~5.0 V minus eFuse drop | within 100 mV at light load | C7 pin 1 / U3 OUT pins | 100–200 mA first power | Rises cleanly after controlled ramp. |
| 3V3 | U4 MP28301 OUT1 | 3.3 V | ±5% initial | TP1 / C9 pin 1 | 100–200 mA first power | 3.135–3.465 V and stable. |
| GND | Board ground | 0 V | n/a | TP2 | n/a | Common reference. |
Procedure:
- Before applying power, measure resistance from VBUS_RAW, 5V_PROT, and 3V3 to GND.
- Apply 5 V with a low current limit.
- Confirm VBUS_RAW, then 5V_PROT, then 3V3 in order.
- Increase current limit to 500 mA after no short/overheat is observed.
- Confirm U3 does not fault during startup and U4 PG1 becomes high.
3. Critical Signal Verification
Table
| Signal | Net | Expected State | Measure At | Notes |
|---|---|---|---|---|
| Reset enable | ESP_EN | High near 3.3 V after RC delay | U1 EN / S1 | Press S1: low; release: high. |
| Boot strap | ESP_BOOT_GPIO9 | High normally | TP5 / S2 | Hold S2: low for bootloader. |
| GPIO8 strap | ESP_GPIO8_STRAP | High | U1 IO8 | Supports USB/JTAG download when GPIO9 low. |
| GPIO2 strap | ESP_GPIO2_STRAP | High | U1 IO2 | Normal boot source strap. |
| eFuse PGOOD | EFUSE_PGOOD | High when 5V_PROT good | U1 IO4 | Pulled to 3V3 by R15. |
| Buck PGOOD | BUCK_PGOOD | High when 3V3 good | U1 IO7 | Pulled to 3V3 by R18. |
4. Connector and Interface Tests
Table
| Connector / Pads | Pins / Nets | Test Method |
|---|---|---|
| J1 USB-C | VBUS_RAW, GND, CC1, CC2, USB_DP, USB_DM | Continuity and USB enumeration. |
| TP1 | 3V3 | Measure 3.3 V after power-up. |
| TP2 | GND | Ground reference. |
| TP3 | UART_TXD0 | Serial activity if firmware uses UART. |
| TP4 | UART_RXD0 | Optional UART input. |
| TP5 | ESP_BOOT_GPIO9 | BOOT strap check. |
5. Programming and Debug
Table
| Interface | Signals | Connector | Tool |
|---|---|---|---|
| Native USB CDC/JTAG | USB_DP GPIO19, USB_DM GPIO18 | J1 USB-C | PlatformIO / esptool.py |
| UART fallback | UART_TXD0, UART_RXD0, GND | TP3/TP4/TP2 | USB-UART adapter at 3.3 V levels |
Procedure:
- Connect USB-C to host.
- If upload fails, hold S2 BOOT, press/release S1 RESET, release S2.
- Run
pio run -t upload. - Open monitor at 115200 baud.
6. Functional Validation
Table
| Test | Components | Input | Expected Output | Pass Criteria |
|---|---|---|---|---|
| USB attach | J1, D2, U1 | USB-C cable | ESP32 enumerates | Host sees ESP32 USB serial/JTAG. |
| 3.3 V regulation | U4, L1, C8–C12 | 5 V input | 3.3 V at TP1 | Stable within tolerance. |
| T/RH read | U1, U2 | Ambient air | Serial/BLE values | Plausible room temp/RH; no I2C errors. |
| Wi-Fi | U1 | Valid SSID/password | IP address and HTTP POST attempts | Connects or reports offline cleanly. |
| BLE | U1 | BLE scanner | TRH-Node advertisement | Environmental service visible. |
| Status LED | U1, R9, LED1 | Firmware blink | LED flashes | LED responds to GPIO3. |
| eFuse current monitor | U3, R14, U1 | Load current | ADC-derived current | Reading changes with load. |
7. Expected Measurements Reference
Table
| Measurement | Location | Expected Value | Instrument |
|---|---|---|---|
| USB VBUS | J1/D1 pin 1 | ~5.0 V | DMM |
| Protected 5 V | C7 pin 1 | ~5.0 V | DMM/scope |
| 3.3 V rail | TP1 | 3.3 V ±5% | DMM/scope |
| EN | U1 EN | 3.3 V normally, 0 V when S1 pressed | DMM |
| BOOT | TP5 | 3.3 V normally, 0 V when S2 pressed | DMM |
| I2C SCL/SDA | U2 pins | 3.3 V idle, clock/data during reads | Scope/logic analyzer |
Pass/Fail Summary
Table
| Test Section | Result | Notes |
|---|---|---|
| Visual Inspection | [ ] Pass / [ ] Fail | |
| Power Rails | [ ] Pass / [ ] Fail | |
| Critical Signals | [ ] Pass / [ ] Fail | |
| USB / Debug | [ ] Pass / [ ] Fail | |
| Sensor | [ ] Pass / [ ] Fail | |
| Wireless | [ ] Pass / [ ] Fail |
Board status: [ ] Ready for enclosure/layout validation / [ ] Requires rework
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signal Verification
4. Connector and Interface Tests
5. Programming and Debug
6. Functional Validation
7. Expected Measurements Reference
Pass/Fail Summary
