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Зараз не можу продовжити інструментами: у акаунті закінчились ACUs, тому AI-дії в проєкті тимчасово недоступні.
Що вже є в проєкті:
  • плата зараз 49 × 43.5 мм, 2-шарова;
  • XT60 (J1) стоїть зліва, повернутий вертикально;
  • JST-XH (J2) стоїть приблизно по центру/правіше, але його ще треба розвернути;
  • pads зараз:
    • P1 = B0−
    • P3 = B4+
    • P4 = B1
    • P2 = B2
    • P5 = B3
  • доріжки були очищені, тобто зараз треба буде прокладати заново;
  • DXF ще треба імпортувати/відтворити як реальну форму плати з прорізами.
Що лишилось зробити, коли ACUs зʼявляться:
  • імпортувати PB.dxf як контур/вирізи плати;
  • зробити прорізи по реальних розмірах DXF, окремо від pads;
  • розвернути J2 JST-XH так, щоб Pin_1 / GND / B0− лишився на правильному пʼятачку;
  • прокласти короткі доріжки від 5 pads до JST/XT60, не автотрасою “куди попало”;
  • перевірити DRC.
Перевір DRC
Імпортуй DXF контур
Розверни J2
Проклади доріжки
Покажи імпорт DXF

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4S1P PCB Geometry and Routing Plan
Reviewed files
  • PB.dxf
  • 4s1p(PB).step
  • PB.step
Mechanical/geometric findings
  • Units are millimeters in both DXF and STEP.
  • DXF board outline is a rectangle approximately 49.0 mm × 43.5 mm.
    • DXF coordinate span: X = -49.0 to 0.0 mm, Y = 0.0 to 43.5 mm.
  • The smaller 4s1p(PB).step matches the DXF-like PCB/contact geometry and appears to represent a board/plate about 2 mm thick.
  • The full PB.step contains product names:
    • PB v3
    • Database v7
    • XT60-M
  • Full model confirms this is more than just the balance board: it includes an XT60-M connector body/reference in the assembly, so the final board may need both balance wiring and a main power interface depending on the intended electrical role.
DXF closed polylines / mechanical geometry
Correction after user review: the narrow/slot-like DXF polylines must not be treated as electrical copper pads by default. They may be mechanical slots/cutouts/reliefs. Electrical pads must only be created from features that are explicitly copper/contact areas in the mechanical model or confirmed by the user.

Table

DXF entityApproximate coordinatesInitial interpretation
101X -49 to 0, Y 0 to 43.5PCB outline
108X -22 to -6, Y 1.2 to 2.3mechanical slit/slot candidate, not an electrical pad unless confirmed
102X -43 to -27, Y 3.2 to 7.3mechanical slit/slot candidate, not an electrical pad unless confirmed
104X -22 to -6, Y 14.2 to 18.3, curved cornermechanical slit/slot candidate, not an electrical pad unless confirmed
103X -43 to -27, Y 14.2 to 16.8, curved cornermechanical slit/slot candidate, not an electrical pad unless confirmed
106X -22 to -6, Y 25.2 to 29.3, curved cornermechanical slit/slot candidate, not an electrical pad unless confirmed
105X -43 to -27, Y 26.7 to 29.3, curved cornermechanical slit/slot candidate, not an electrical pad unless confirmed
107X -43 to -27, Y 36.2 to 40.3mechanical slit/slot candidate, not an electrical pad unless confirmed
100X -22 to -6, Y 41.2 to 42.3mechanical slit/slot candidate, not an electrical pad unless confirmed
4S balance wiring model
A 4S battery needs 5 balance nodes:
  1. B0 / B- — cell 1 negative
  2. B1 — cell 1 positive / cell 2 negative
  3. B2 — cell 2 positive / cell 3 negative
  4. B3 — cell 3 positive / cell 4 negative
  5. B4 / B+ — cell 4 positive
The PCB should route each confirmed cell node to a 5-pin balance connector. These lines should be treated as sense/balance lines, not high-current discharge paths, unless the user confirms otherwise.
Electrical and safety recommendations
  • User-confirmed requirements:
    • Main power current flows only through pack B+ and B- to/from the XT60.
    • Nominal main current: 60 A.
    • Short-duration current: 100 A for up to 3 minutes.
    • Cell-to-cell series connections are welded directly between packs, not carried through PCB traces.
    • Balance connector current target: up to 2 A.
    • Acceptable power-section temperature: up to 45°C.
    • Copper thickness is to be selected by design, with reinforcement by busbars/wires acceptable if needed.
  • Do not route main battery charge/discharge current through thin PCB traces unless the exact current is specified and the copper thickness/temperature rise are sized for it.
  • If this board only brings out balance leads, traces can be modest width, but each balance line should still tolerate fault conditions from a battery pack.
  • Consider adding per-line series protection: small resistors, fusible links, or PTCs depending on BMS/charger expectations.
  • Keep exposed copper weld pads isolated with generous soldermask/copper clearance between adjacent cell potentials.
  • Exposed weld pads should be explicitly defined as soldermask openings; surface finish and plating must match the laser-welding process.
High-current copper recommendation
For 60 A nominal and 100 A for 3 minutes, plain narrow PCB traces are not appropriate. The preferred design is:
  • Use 4 oz copper if the manufacturer can support it.
  • Route B+ and B- as very large copper pours on both top and bottom layers, not as thin traces.
  • Stitch top and bottom copper with many vias along the current path.
  • Leave soldermask openings over the high-current pours so they can be reinforced with solder, copper braid, copper wire, or a shaped busbar if thermal testing requires it.
  • Treat the PCB copper as the geometry/current-spreading layer and design in a clear reinforcement option from the start.
If the available copper width is limited by the 49 mm × 43.5 mm board, reinforcement should be considered mandatory for reliable 100 A pulse operation.
IPC-2221 rough width estimate
Approximation used: external trace/pour equation I = 0.048 × ΔT^0.44 × A^0.725, where A is copper cross-section in mil². This is a rough sizing check only; final high-current battery hardware still needs thermal validation.
Assuming 25°C ambient and 45°C maximum allowed copper temperature gives roughly 20°C temperature rise.

Table

CurrentCopperSingle-layer width at ΔT≈20°CTop+bottom shared, width per side at ΔT≈20°C
60 A2 oz28.0 mm10.7 mm
60 A3 oz18.6 mm7.2 mm
60 A4 oz14.0 mm5.4 mm
100 A2 oz56.6 mm21.7 mm
100 A3 oz37.7 mm14.5 mm
100 A4 oz28.3 mm10.9 mm
Design selection: 4 oz copper, top+bottom parallel pours, with each high-current rail given at least about 11 mm effective width per side in the narrowest continuous section if possible. Because 100 A is only a 3-minute pulse, this is a reasonable starting point, but any narrower bottleneck should be reinforced with soldered copper wire/braid/busbar.
Recommended practical implementation:
  • Use 4 oz, 2-layer PCB.
  • Make B+ and B- as large copper pours on both sides.
  • Keep the narrowest continuous effective copper width per rail close to or above 11 mm per side near XT60 and weld pads.
  • Add dense via stitching between layers along the full current path.
  • Add open-soldermask reinforcement zones so copper wire/braid/busbar can be soldered after fabrication if temperature testing is too high.
  • Balance lines up to 2 A can use normal traces, e.g. about 0.5–1.0 mm depending on available space, with adequate clearance from high-current copper.
Items required before generating the actual schematic/layout
  1. Confirm the balance connector type and footprint:
    • common default: JST-XH 5-pin, 2.54 mm pitch;
    • alternative: JST-PH 5-pin, 2.0 mm pitch;
    • or another connector specified by part number.
  2. Confirm connector pin order/orientation on the board:
    • proposed default: B- / B0, B1, B2, B3, B+ / B4.
  3. Identify the actual copper/contact areas separately from mechanical slots/cutouts. Do not use the slot geometry as pads.
  4. Confirm cell chemistry and maximum pack voltage/current.
  5. Confirm laser-welding stack-up: nickel strip to copper, nickel-plated copper, separate busbar, or another process.
Proposed default implementation after confirmation
  • Use the 49.0 mm × 43.5 mm DXF outline as the PCB contour.
  • Create mechanical slots/cutouts from slot geometry, and create copper pads only where the 3D model or user markup identifies actual electrical contacts.
  • Add a 5-pin JST-XH balance connector unless another connector is specified.
  • Route five balance nets from the correct pad/node sequence to the connector.
  • Route B+ and B- to XT60 using maximal top/bottom copper pours with via stitching and intentional reinforcement windows.
Correction status
  • The previous layout attempt was reverted because it moved connectors and incorrectly used slot geometry as electrical pads.
  • The project is back to an empty schematic/layout state, keeping only the project name, description, and planning notes.
  • Next implementation must preserve connector locations from the mechanical model and keep slots/cutouts mechanical unless explicitly identified as copper.
Current corrected implementation
  • Corrected per user clarification:
    • Slots/prorezi are mechanical only and are not connected to nets.
    • There are exactly 5 weld pads: P1…P5, one for each 4S node.
    • Traces are routed from the weld pads, not from the slots.
    • XT60 is rotated 90° as in the 3D model to minimize the high-current path from weld pads to XT60.
  • Board outline: 49 mm × 43.5 mm, 2-layer.
  • Mechanical slots added as separate HOLE/cutout pads named SLOT_*_MECH_ONLY.
  • Weld pad assignment:
    • P1 = B0_B-.
    • P2 = B1.
    • P3 = B2.
    • P4 = B3.
    • P5 = B4_B+.
  • Weld pad size: about 6 mm × 3 mm, exposed copper with solder mask expansion.
  • Connector placement:
    • J1 XT60-M rotated 90°.
    • J2 JST-XH placed on the right side for balance routing.
  • Routing completed from the 5 pads to J2, with B0_B- and B4_B+ also connected to XT60.
  • Current DRC check reports no open ERROR/WARNING checks for airwires, overlapping copper, invalid layer, dangling trace, under-connected via, component overlap/outside-board, or missing footprints.
Latest placement correction from user
  • User clarified the mechanical intent:
    • There must be 5 weld pads total, not 8.
    • The slots/prorezi are separate mechanical features and must not be used as pads.
    • Three weld pads sit near the XT60.
    • The JST-XH connector sits between the other two weld pads.
    • XT60 is intentionally rotated 90° in the 3D model to minimize the high-current distance from weld pads to XT60.
  • Implemented accordingly:
    • J1 XT60-M is vertical/90°.
    • P1, P2, P3 are placed near XT60.
    • J2 JST-XH is on the right side between P4 and P5.
    • Mechanical slot objects remain separate and unconnected.
  • Updated net mapping for this placement:
    • P1 = B0_B-.
    • P2 = B4_B+.
    • P3 = B1.
    • P4 = B2.
    • P5 = B3.
  • Routing was redone. Latest DRC reports no open ERROR/WARNING checks for the checked categories.
Latest correction after user review
  • Corrected pad-to-net assignment per user:
    • P1 = B0_B- / minus.
    • P3 = B4_B+ / plus.
    • P4 = B1.
    • P2 = B2.
    • P5 = B3.
  • User manually adjusted pad positions; those positions are preserved.
  • Slots/prorezi were re-applied using the real DXF bounding dimensions and remain mechanical-only, not connected to any net.
  • Layout is a top-side view in Flux. No intentional mirroring was applied; if comparing to the underside/bottom view, it will visually appear mirrored.
  • User rejected the previous automatic routing pathing, so all routed traces were cleared.
  • J1 XT60 was rotated to the opposite 90° orientation (270°) to match the intended 3D model direction.
  • Current state intentionally has unrouted airwires; mechanical checks for overlaps/outside-board/missing footprints are clean in the latest check.
Remaining caution
This is still an approximate implementation based on the visible 3D/screenshot geometry. Before fabrication, visually compare pad/slot placement to the 3D model and adjust pad centers if the bent contacts land slightly differently. For 60–100 A, reinforce B0_B- and B4_B+ with copper wire/busbar or convert to wider pours before manufacturing.
Current 2-layer implementation attempt
  • Rebuilt the schematic using only real electrical nodes:
    • J1 = XT60-M main connector.
    • J2 = JST-XH 5-pin balance connector.
    • P1…P5 = separate small electrical pickup pads for B0_B-, B1, B2, B3, B4_B+.
  • The DXF slot geometry is now implemented as mechanical HOLE/cutout objects, not connected to any net.
  • Board outline is 49.0 mm × 43.5 mm, 2-layer stackup.
  • Estimated connector placement from PB.step:
    • JST-XH placed near the location extracted from the model.
    • XT60 placed at the right-edge power-connector position; exact overhang/mechanical fit still needs visual confirmation.
  • Routing status:
    • Balance nets B1, B2, B3 routed at 0.75 mm.
    • B0_B- and B4_B+ routed with wider 4 mm baseline traces to/from XT60 plus 0.75 mm sense branches to JST.
    • DRC after this pass reports no open ERROR/WARNING checks for the checked categories.
User-marked weld pad update
  • User clarified that the blue rectangles in the screenshot are approximate weld pad locations, and the blue lines show intended routing directions.
  • The previous mechanical HOLE/cutout objects at those rectangles were removed.
  • Implemented 8 exposed rectangular weld pads P1…P8, approximately matching the DXF/user-marked rectangles:
    • Pad size: about 16 mm × 3 mm.
    • Solder mask expansion: 0.1 mm so the pads are exposed for welding/lugging/reinforcement.
    • Direct copper connection enabled.
  • Net assignment:
    • P1 = B0_B-.
    • P2 = B1.
    • P3 and P4 = B2.
    • P5 and P6 = B3.
    • P7 and P8 = B4_B+.
  • XT60 was moved to the left side and JST-XH near the right-center to match the user screenshot more closely.
  • Routing was redone after the pad update; DRC currently reports no open ERROR/WARNING checks for airwires, overlapping copper, invalid layers, dangling traces, under-connected vias, component overlap/outside-board, or missing footprints.
Remaining mechanical/electrical caution
This is a cleaner 2-layer baseline, but the exact copper pickup pad locations are still provisional because the provided DXF primarily identifies slots/cutouts and does not unambiguously label the intended copper contact regions. Before fabrication:
  • visually confirm the connector positions against the STEP model;
  • visually confirm whether P1…P8 align with the intended real weld locations from the mechanical model;
  • replace the 4 mm baseline power traces with larger copper pours or soldered copper wire/busbar reinforcement for 60 A nominal / 100 A pulse operation.

  • Reviewed files

  • Mechanical/geometric findings

  • DXF closed polylines / mechanical geometry

  • 4S balance wiring model

  • Electrical and safety recommendations

  • High-current copper recommendation

  • IPC-2221 rough width estimate

  • Items required before generating the actual schematic/layout

  • Proposed default implementation after confirmation

  • Correction status

  • Current corrected implementation

  • Latest placement correction from user

  • Latest correction after user review

  • Remaining caution

  • Current 2-layer implementation attempt

  • User-marked weld pad update

  • Remaining mechanical/electrical caution

Documents

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4S1P Battery Power Board

4S1P Battery Power Board thumbnail
4S1P Li-ion/LiPo battery interface board with XT60 high-current output, JST-XH 5-pin balance connector, exposed weld/contact pads, and 4 oz 2-layer high-current copper pours for 60 A nominal / 100 A pulse operation.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$0.11–$0.19

Digi-Key

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HQonline

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LCSC

$0.10

Mouser

$0.20

TME

$0.92

Verical

$0.10–$0.51

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