USB-C Programming Adapter Design
0:29
Researching manual options.
Reading docs about How do I mark USB D+ and D- as a controlled impedance pair in Flux? Specifically which inspector properties should be set for the terminals, such as Bus Group, Pair Role, and Controlled Impedance Pair?.
I can’t apply terminal-level controlled-impedance properties directly with my current edit tools.
This is the most relevant entry I found related to the topic:
Defined at terminal level
- Bus Group: this property defines the different differential pairs. Some interfaces might require many different bus groups (like ethernet), while others only require one (like USB2.0). For example, if a microcontroller contains two USB buses, terminals for one bus should contain “Bus Group” = USB_1 and terminals in the second bus should contain “Bus Group” = USB_ 2
- Pair Role: defines what type of role the terminal has. For example CLK, D1, D2, D3, D4, TX, TX1, TX2, TX3, RX, RX1, RX2, RX3, etc.
- Controlled Impedance Pair: this should be a unique name that identifies the pair. This is particularly important for parts that contain more than one bus. For example in a part with two USB buses, you will have two Data 1 pairs. In that case one pair could be named “Data1_Bus1” and the other pair “Data1_Bus2”. You can follow any naming convention you prefer, the only requirement is that each pair has a unique “Controlled Impedance Pair” string.
How do I set J1
Show USB pair fields
Set USB bus names
16 days
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Project Specification
Design Summary
Status: Approved
Manufacturing target: Prototype
Software / firmware: ESP32-S3 native USB-Serial/JTAG adapter, no onboard firmware required
Scope
Purpose
This board is a compact USB-C to TC2030 programming and debug adapter for ESP32-S3 targets using native USB-Serial/JTAG. Revision A1 focuses on a simple, non-powered adapter that protects the USB data pair while keeping the target-supplied 3.3 V rail isolated from USB VBUS.
In scope
- USB-C receptacle interface with USB2 D+ and D- routing
- CC1 and CC2 5.1 kOhm pull-down resistors for USB-C device role
- USBLC6-2SC6 ESD protection on USB D+ and D-
- VBUS indicator LED and local 100 nF VBUS decoupling
- Manual reset button with 10 kOhm pull-up to target 3.3 V and 100 nF capacitor across switch
- Target header J2 and debug header J3 pinout implementation
- 2-layer PCB with JLCPCB-compatible constraints and required silkscreen markings
Out of scope
- Onboard 3.3 V regulation from USB VBUS
- USB-UART bridge or any active protocol conversion
- Automatic boot/reset sequencing circuitry
- Enclosure-specific mounting features
System context
This adapter sits between a USB host and an ESP32-S3 target board. The host connects through USB-C. Protected USB D+ and D- and target power reference are delivered to a compact TC2030-compatible target header, while a separate debug header exposes unprotected USB data, VBUS, reset, 3.3 V reference, and ground.
Key interfaces
- USB-C host connection through J1
- Protected target programming/debug connection through J2
- Auxiliary debug breakout through J3
- Manual reset through SW1 on the shared RST net
Attach: simple block diagram
Diagram
Requirements
Functional
- The board shall provide a USB-C receptacle for connection to a host computer.
- The board shall support ESP32-S3 flashing and debugging over native USB-Serial/JTAG.
- The board shall route USB D+ and D- through an ESD protection device before reaching target header J2.
- The board shall expose unprotected D+ and D- on debug header J3.
- The board shall include a manual reset button on the RST net.
- The board shall include a visible green LED that indicates presence of VBUS.
Electrical
- USB-C CC1 and CC2 shall each use 5.1 kOhm pull-downs to GND.
- VBUS shall connect only to the ESD device VBUS pin, the VBUS LED path through 1 kOhm, the 100 nF decoupling capacitor, and J3 pin 1.
- +3V3 shall enter only from J2 pin 1 and shall not be tied to VBUS.
- Reset network shall use a 10 kOhm pull-up from RST to +3V3.
- Reset switch bypass capacitor shall be 100 nF connected across SW1.
- J2 pin order shall be: +3V3, protected D-, RST, protected D+, GND, GND.
- J3 pin order shall be: VBUS, unprotected D+, unprotected D-, RST, +3V3, GND.
Mechanical / environmental
- Board size target is approximately 30 mm x 20 mm.
- Layout shall use a 2-layer stackup.
- USB-C connector shall be placed on the left edge.
- J2 shall be on the right edge.
- J3 shall be placed along a long board edge.
- Reset switch shall be accessible near a board edge.
Key constraints
- JLCPCB-compatible manufacturing constraints and assembly-friendly footprints are required where practical.
- ESD device must be placed very close to the USB-C connector.
- CC pull-down resistors must be adjacent to the CC pins.
- Bottom layer shall be used as a ground pour reference.
- USB D+ and D- shall be routed with controlled-impedance intent, kept short and parallel.
- Silkscreen shall include the title FENO USB PROGRAMMER A1, reference designators, and pin-1 markers.
Dependencies and risks
Dependencies
- Library availability of exact connector, ESD array, headers, LED, and switch footprints
- JLCPCB assembly compatibility for selected parts
Key risks
- Incorrect USBLC6-2SC6 signal-side orientation could swap protected and connector-side routing.
- Tight board size may constrain connector and header placement if footprints are larger than expected.
- A 2-layer stackup makes USB routing more sensitive to return-path continuity than a 4-layer design.
Validation
Success criteria
- All specified components are placed and correctly connected.
- VBUS remains isolated from +3V3 except through explicit header exposure rules.
- USB-C, ESD protector, target header, debug header, LED path, and reset network match the approved pinout and values.
- Layout satisfies edge-placement constraints and includes bottom ground pour intent.
- Export outputs are ready for JLCPCB-compatible fabrication and assembly review.
Planned checks
- Schematic pin-to-pin verification against required net list
- Review of PCB board size, stackup, and component edge placement
- DRC and airwire review before export
- Export of Gerber, BOM, pick-and-place, and PCB PDF outputs
Release-facing notes
Expected deliverables
- Schematic
- PCB layout
- BOM export
- Pick-and-place export
- Gerber manufacturing package
- PCB PDF export
Special release notes
- USB-C receptacle is specified as HRO TYPE-C-31-M-12.
- ESD protector is specified as USBLC6-2SC6.
- 3.3 V is target-supplied only and must not be back-powered from USB.
Change notes / open questions
Changes in this revision
- Initial A1 definition created for a compact USB-C to TC2030 programmer adapter.
- Approved pinout, protection strategy, and placement constraints captured.
Open questions
- Final exact JLCPCB-friendly part selections for headers, LED, and tactile reset switch to be finalized during implementation.
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