PCB Assembly Challenges

flux

Prepared the JLCPCB PCB planning handoff package. Important: the current layout is intentionally unfinished and contains airwires, dangling/floating copper, and local overlaps; the handoff brief tells JLCPCB not to fabricate until they finish routing and achieve clean DRC.
Send JLCPCB the handoff brief first, then these files and the editable Flux project URL. Ask them to return clean final Gerbers, BOM/CPL, and a DRC report after completing the U1/jumper area.
Complete handoff documentation
Export DRC violations
Audit JLC BOM
Document jumper mappings
Run final ERC
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Files

Schematic

Layout

3D View

JLCPCB PCB Planning Handoff
Project
  • Board: TMCC WiFi DCC 5A Module / WIFI to DCC Board. Ver 2.0
  • Current outline: approximately 29 mm × 93 mm, fixed width; small further length adjustment only if absolutely necessary.
  • Purpose: Accept 14–24 VAC nominal/max, up to 30 VDC, or approximately 22–24 V DCC input; generate a bipolar DCC output using ESP32 and DRV8873.
  • Target regenerated power rail: 16.8 V nominal. Output-current design target: 5 A, subject to thermal and low-line validation.
Important Status
This is an unfinished layout handoff, not a released manufacturing package. Do not fabricate from the supplied Gerbers without completing routing and obtaining a clean DRC.
Current fresh DRC reports:
  • 14 airwire endpoint findings
  • 4 dangling trace findings
  • 1 floating copper trace (Trace 11f3)
  • 29 overlapping-copper findings
Most errors are in the U1/jumper-rework area created during the latest unfinished zero-ohm jumper placement. The JLCPCB planning engineer should delete stale/overlapping local copper, complete the intended jumper connections, refill planes, and rerun full DRC.
Required Layout Completion
  1. Preserve all circuitry and the present board width.
  2. Complete the three intended 0-ohm jumper functions near U1:
    • U1 nITRIP to R7 ground-side connection
    • U1 nITRIP to C13 ground-side connection
    • U1 VCP to C15 pin 1
  3. The jumpers are intended as JLC-assembled 0603 0-ohm resistors using LCSC C95177; confirm their schematic/net mapping before routing.
  4. Remove stale local traces and accidental copper/via overlaps around the jumpers/U1 before routing.
  5. Keep DCC_SIG, DRV_VCP, and DRV_SR in the low-current rule class: 0.15 mm trace / 0.15 mm clearance.
  6. Do not narrow the high-current nets to solve congestion. Preserve or improve wide copper for VBUS, 16V_DCC, DCC_A, DCC_B, AC input, and GND return.
  7. Keep continuous inner GND planes and outer GND fills; refill and verify after routing.
  8. Add/retain thermal vias beneath exposed power pads as allowed by assembly process and footprint requirements.
  9. Preserve ESP32 antenna keepout and Tag-Connect access.
  10. Confirm J1/F1 mechanical clearance and keep the reduced C1 footprint.
Input and Power Design Constraints
  • Input range: 14–24 VAC; also up to 30 VDC or approximately 22–24 V DCC.
  • C1: LKME5001J102MF, LCSC C442960, 1000 µF / 50 V, radial 10 mm diameter / 5 mm pitch; now intended for normal JLC assembly rather than manual installation.
  • U3: LMR36015BRNXR, LCSC C1850340, 60 V-input 3.3 V regulator.
  • U5: LM5146-Q1-based 16.8 V buck stage.
  • U1: DRV8873HPWPRQ1, LCSC C2150479.
  • Q1/Q2: SED10070GG, LCSC C396083.
  • L2: LCSC C2047831.
  • ESP32 module: LCSC C701346.
  • The 1000 µF capacitor does not guarantee continuous 16.8 V / 5 A regulation at the lowest 14–18 VAC input; low-line dropout and ripple must be validated on prototypes.
Connectors and Indicators
  • J1 is AC/non-polar input; silkscreen must remain AC~ AC~, not +/-.
  • J2 is bipolar DCC output; label DCC A and DCC B, not fixed polarity.
  • J3 is a TC2030-IDC-NL Tag-Connect footprint with IO0, RX, TX, 3V3, GND, EN.
  • LED1: red power LED, LCSC C2286.
  • LED2: blue activity LED, LCSC C2288, controlled by ESP32 GPIO16.
Final Acceptance Criteria
  • Zero airwires.
  • Zero dangling traces and floating copper.
  • Zero copper overlaps/shorts between different nets.
  • Zero missing footprints, invalid layers, component-body overlaps, or components outside the board.
  • Full plane refill and GND connectivity verified.
  • High-current path/current-density and thermal review completed for 5 A operation.
  • BOM and CPL match current design and use JLC/LCSC parts; J3 is footprint-only and excluded from assembly.
  • C1 is included in BOM and CPL.
  • Confirm polarity/orientation for C1, all diodes, LEDs, U1, U3, U5, Q1/Q2, and ESP32 module.
  • Deliver final Gerbers, drill files, JLC BOM, CPL, and updated source/layout files after clean DRC.
Notes to Planning Engineer
The supplied manufacturing/design exports represent the current editable state and are reference inputs for finishing the layout. Please treat the DRC report and this brief as authoritative indicators that the current Gerbers are not release-ready.

  • Project

  • Important Status

  • Required Layout Completion

  • Input and Power Design Constraints

  • Connectors and Indicators

  • Final Acceptance Criteria

  • Notes to Planning Engineer