Diseño de PCB para Raspberry Pi CM4
Thought
Work completed
- Project description updated to detail PCIe cellular slot integration
- System architecture property set with CM4, PCIe slot, power, USB, SIM, and antenna subsystems
- J3 placed with mounting holes and keep-out zone
- Ground portal symbol added
- U1 ESD array added for SIM/UIM
- U2 switched 3.3 V rail controller with enable/reset
- C1 and C2 decoupling capacitors placed
- D1 and D2 TVS diodes added at regulator output and connector power pins
Tasks remaining
- Select and place AC-coupling Capacitor and Common-mode Choke for PCIe/USB lanes
- Select and add Nano-SIM Holder and u.FL Connector
- Connect all nets:
- PCIe differential pairs, REFCLK, PERST# via AC-coupling & chokes
- USB2.0 D+/D– from hub to socket
- SIM/UIM through ESD array to nano-SIM holder
- 3.3 V rail and enable/reset to socket and regulator
- Review schematic for completeness and electrical requirements
- Verify passive/active ratings and footprints
- Configure PCB stackup, copper layers, and ground fill
- Define mechanical mounting holes and clearance
- Perform DRC and length-match checks
Success criteria
- The PCIe slot socket is placed but nets aren’t yet routed; supporting I/O, power, SIM, and antenna connectors are pending. Signal-integrity, EMI/ESD compliance, and board-size fit remain to be validated.
Next step
Pick and add the AC-coupling capacitors and common-mode chokes for the PCIe and USB lanes.
Flux stopped
