IC1 Pin Description and Usage
Worked for 1 min 15 sec
Created the IC1 pin description file for the ESP32-S3-WROOM-1-N4R8, including functions, I/O behavior, strapping/boot notes, USB/JTAG/UART considerations, and project-observed connections.
File:
/files/ic1-pin-description-esp32-s3-wroom-1-n4r8~m5
make a pinout map for GPIOs on the IC1 for firmware developer
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I’ll build a firmware-facing GPIO pinout map for IC1, using the schematic connections plus ESP32-S3 pin restrictions, and save it as a project file.
Worked for 52 sec
Created the firmware-facing GPIO pinout map for IC1 / ESP32-S3-WROOM-1-N4R8, including C-style pin constants, active levels, schematic connections, and restricted pins.
File:
/files/ic1-firmware-gpio-pinout-map~8tReview and update docs
Run schematic ERC
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Check boot pins
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IC1 Pin Description — ESP32-S3-WROOM-1-N4R8
IC1 is an Espressif ESP32-S3-WROOM-1-N4R8 module. It contains an ESP32-S3 SoC with integrated flash/PSRAM module resources and a PCB antenna. All digital GPIOs are 3.3 V domain unless otherwise constrained by the module variant and internal flash/PSRAM connections. Avoid applying voltages above 3.3 V to GPIOs.
Pin type legend from the Espressif module datasheet: P = power, I = input, O = output, T = high impedance/tri-state capable.
General usage notes
- 3V3 power: Provide a stable 3.3 V rail with adequate bulk and local decoupling for Wi-Fi current bursts.
- Grounding: Connect all GND pins and the exposed pad/center ground pads to the ground plane with short, low-impedance vias.
- EN / CHIP_PU: Must not float. Use a pull-up to 3V3 and optional small capacitor to GND for reset noise immunity.
- Strapping pins: GPIO0, GPIO3, GPIO45, and GPIO46 are sampled at reset. External circuitry must not force invalid boot states during reset.
- Boot mode: For normal SPI flash boot, GPIO0 should be high at reset. Pull GPIO0 low during reset to enter download boot, with GPIO46 low or default.
- USB pins: GPIO19 and GPIO20 are USB D−/D+ and are used by USB Serial/JTAG by default. Reusing them as GPIO disables that function.
- JTAG pins: GPIO39–GPIO42 are JTAG-capable; avoid conflicting external loads if JTAG debugging is needed.
- UART0 pins: TXD0/GPIO43 and RXD0/GPIO44 are the default serial console/programming UART pins.
- Octal PSRAM restriction: This module is N4R8, so it includes 8 MB Octal PSRAM. ESPressif notes IO35, IO36, and IO37 are connected to Octal SPI PSRAM and are not available for other uses.
- Antenna keepout: Keep copper, traces, components, and ground pour out of the module antenna keepout area per Espressif layout guidelines.
Pin-by-pin table
Table
| Module pin | Symbol pin name in project | Type | Primary / alternate functions | Input/output characteristics | Special considerations |
|---|---|---|---|---|---|
| 1 | GND_1 | P | Ground | Power return | Tie directly to ground plane. |
| 2 | 3V3 | P | 3.3 V module supply | Power input | Needs stable 3.3 V supply and decoupling; design for Wi-Fi burst current. |
| 3 | EN | I | Chip enable / reset input | High = module enabled; low = powered down/reset | Do not leave floating. Pull up to 3V3; capacitor to GND can improve reset immunity. |
| 4 | IO4 | I/O/T | RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3 | 3.3 V bidirectional GPIO; RTC/touch/ADC capable | Good general GPIO/ADC/touch pin. Avoid overvoltage; consider ADC source impedance. |
| 5 | IO5 | I/O/T | RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4 | 3.3 V bidirectional GPIO; RTC/touch/ADC capable | Good general GPIO/ADC/touch pin. |
| 6 | IO6 | I/O/T | RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5 | 3.3 V bidirectional GPIO; RTC/touch/ADC capable | Good general GPIO/ADC/touch pin. |
| 7 | IO7 | I/O/T | RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6 | 3.3 V bidirectional GPIO; RTC/touch/ADC capable | Good general GPIO/ADC/touch pin. |
| 8 | IO15 | I/O/T | RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P | 3.3 V GPIO; ADC2; UART0 RTS; optional 32 kHz crystal pin | Avoid loading if using 32 kHz crystal function. ADC2 availability can be affected by firmware/peripheral use. |
| 9 | IO16 | I/O/T | RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N | 3.3 V GPIO; ADC2; UART0 CTS; optional 32 kHz crystal pin | Avoid loading if using 32 kHz crystal function. |
| 10 | IO17 | I/O/T | RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6 | 3.3 V GPIO; UART1 TX; ADC2 | General GPIO/UART/ADC2. |
| 11 | IO18 | I/O/T | RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, CLK_OUT3 | 3.3 V GPIO; UART1 RX; ADC2; clock output | General GPIO/UART/ADC2; avoid unintended clock output conflicts. |
| 12 | IO8 | I/O/T | RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7, SUBSPICS1 | 3.3 V GPIO; touch/ADC1; SPI alternate | Good general GPIO/ADC/touch pin; can be SPI chip-select if configured. |
| 13 | IO19 | I/O/T | RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D− | 3.3 V GPIO; USB D− capable | Reserved for USB Serial/JTAG or USB OTG if used; route as USB differential pair with IO20. |
| 14 | IO20 | I/O/T | RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+ | 3.3 V GPIO; USB D+ capable | Reserved for USB Serial/JTAG or USB OTG if used; route as USB differential pair with IO19. |
| 15 | IO3 | I/O/T | RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2 | 3.3 V GPIO; touch/ADC1 | Strapping pin for JTAG signal source. Avoid external circuits that force reset-time levels unintentionally. |
| 16 | IO46 | I/O/T | GPIO46 | 3.3 V GPIO | Strapping pin. Default weak pull-down. Used with GPIO0 for boot mode and can control ROM message behavior; avoid pulling high/low incorrectly at reset. |
| 17 | IO9 | I/O/T | RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD, SUBSPIHD | 3.3 V GPIO; touch/ADC1; SPI alternate | General GPIO; can conflict with SPI alternate functions if firmware config uses them. |
| 18 | IO10 | I/O/T | RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4, SUBSPICS0 | 3.3 V GPIO; touch/ADC1; SPI alternate | General GPIO; SPI alternate available. |
| 19 | IO11 | I/O/T | RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5, SUBSPID | 3.3 V GPIO; touch/ADC2; SPI alternate | General GPIO; ADC2 caveats apply. |
| 20 | IO12 | I/O/T | RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6, SUBSPICLK | 3.3 V GPIO; touch/ADC2; SPI clock alternate | General GPIO; avoid loading if used as high-speed SPI clock. |
| 21 | IO13 | I/O/T | RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7, SUBSPIQ | 3.3 V GPIO; touch/ADC2; SPI alternate | General GPIO; ADC2/SPI caveats apply. |
| 22 | IO14 | I/O/T | RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS, SUBSPIWP | 3.3 V GPIO; touch/ADC2; SPI alternate | General GPIO; avoid conflict if used as SPI write-protect/DQS. |
| 23 | IO21 | I/O/T | RTC_GPIO21, GPIO21 | 3.3 V GPIO; RTC-capable | General GPIO; no ADC/touch listed. |
| 24 | IO47 | I/O/T | SPICLK_P_DIFF, GPIO47, SUBSPICLK_P_DIFF | 3.3 V GPIO on this N4R8 module; differential SPI clock alternate | General GPIO, but note special SPI differential clock alternate function. |
| 25 | IO48 | I/O/T | SPICLK_N_DIFF, GPIO48, SUBSPICLK_N_DIFF | 3.3 V GPIO on this N4R8 module; differential SPI clock alternate | General GPIO, but note special SPI differential clock alternate function. |
| 26 | IO45 | I/O/T | GPIO45 | 3.3 V GPIO | Strapping pin. Default weak pull-down. For non-PSRAM/non-eFuse cases it can affect VDD_SPI voltage; avoid pulling high at reset unless intentional. |
| 27 | IO0 | I/O/T | RTC_GPIO0, GPIO0 | 3.3 V GPIO; RTC-capable | Boot strapping pin. Default weak pull-up. Low at reset enters download boot; do not add large capacitance. |
| 28 | IO35 | I/O/T | SPIIO6, GPIO35, FSPID, SUBSPID | 3.3 V GPIO/SPI-capable in generic table | Not available for other use on ESP32-S3R8 / N4R8 modules because connected to Octal PSRAM. |
| 29 | IO36 | I/O/T | SPIIO7, GPIO36, FSPICLK, SUBSPICLK | 3.3 V GPIO/SPI-capable in generic table | Not available for other use on ESP32-S3R8 / N4R8 modules because connected to Octal PSRAM. |
| 30 | IO37 | I/O/T | SPIDQS, GPIO37, FSPIQ, SUBSPIQ | 3.3 V GPIO/SPI-capable in generic table | Not available for other use on ESP32-S3R8 / N4R8 modules because connected to Octal PSRAM. |
| 31 | IO38 | I/O/T | GPIO38, FSPIWP, SUBSPIWP | 3.3 V GPIO; SPI alternate | Usable GPIO; can be SPI write-protect alternate. |
| 32 | IO39 | I/O/T | MTCK, GPIO39, CLK_OUT3, SUBSPICS1 | 3.3 V GPIO; JTAG MTCK; clock/SPI alternate | Avoid loading/conflict if JTAG debugging is needed. |
| 33 | IO40 | I/O/T | MTDO, GPIO40, CLK_OUT2 | 3.3 V GPIO; JTAG MTDO; clock output | Avoid loading/conflict if JTAG debugging is needed. |
| 34 | IO41 | I/O/T | MTDI, GPIO41, CLK_OUT1 | 3.3 V GPIO; JTAG MTDI; clock output | Avoid loading/conflict if JTAG debugging is needed. |
| 35 | IO42 | I/O/T | MTMS, GPIO42 | 3.3 V GPIO; JTAG MTMS | Avoid loading/conflict if JTAG debugging is needed. |
| 36 | RXD0 | I/O/T | U0RXD, GPIO44, CLK_OUT2 | 3.3 V GPIO; default UART0 RX input | Used for serial bootloader/programming and console receive; keep accessible via programming header. |
| 37 | TXD0 | I/O/T | U0TXD, GPIO43, CLK_OUT1 | 3.3 V GPIO; default UART0 TX output | Used for serial bootloader/programming and console transmit; keep accessible via programming header. |
| 38 | IO2 | I/O/T | RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1 | 3.3 V GPIO; touch/ADC1 | Good general GPIO/ADC/touch pin. In this project it appears connected to SW1. |
| 39 | IO1 | I/O/T | RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0 | 3.3 V GPIO; touch/ADC1 | Good general GPIO/ADC/touch pin. |
| 40 | GND_2 | P | Ground | Power return | Tie to ground plane. |
| 41 | GND_3 | P | Exposed/center ground pad equivalent | Power return and thermal/RF ground | Stitch to ground plane with vias. |
| 42 | GND_4 | P | Ground pad | Power return | Stitch to ground plane. |
| 43 | GND_5 | P | Ground pad | Power return | Stitch to ground plane. |
| 44 | GND_6 | P | Ground pad | Power return | Stitch to ground plane. |
| 45 | GND_7 | P | Ground pad | Power return | Stitch to ground plane. |
| 46 | GND_8 | P | Ground pad | Power return | Stitch to ground plane. |
| 47 | GND_9 | P | Ground pad | Power return | Stitch to ground plane. |
| 48 | GND_10 | P | Ground pad | Power return | Stitch to ground plane. |
| 49 | GND_11 | P | Ground pad | Power return | Stitch to ground plane. |
IC1 connections observed in this project
- 3V3 is connected to the main 3.3 V rail shared with U2, U3 output, capacitors, LEDs, and PROG pin 1.
- EN is connected to R5 and PROG pin 6.
- IO0 is connected to PROG pin 5 for boot/download control.
- RXD0/TXD0 are connected to PROG pins 3/4 for programming UART.
- IO9 is connected to U2 D/C.
- IO12 is connected to U2 CLK.
- IO2 is connected to SW1.
- IO4 is connected through R4.
- All listed GND pins are connected to the project GND net.
Sources
- Espressif ESP32-S3-WROOM-1 / ESP32-S3-WROOM-1U Datasheet, Pin Definitions and Boot Configurations.
- Espressif ESP32-S3 GPIO documentation and hardware design guideline notes for strapping pins.
General usage notes
Pin-by-pin table
IC1 connections observed in this project
Sources
