3D Enclosure Design

V

vasy_skral

make a 3d model for enclosure for this project

flux

I’ll inspect the PCB and connector geometry, create a manufacturable enclosure concept and CAD model, then verify board fit and access openings.

flux

I’m measuring the finished board now so the enclosure proposal is based on the actual outline, controls, connectors, and assembly clearances.

flux

I measured a 64 × 54 × 1.3 mm board with four exposed Cherry MX keys, a large e-paper display, four indicator LEDs, BAT1 terminal block, BAT2 battery header, and PROG header; there are no dedicated mounting holes.
Proposed enclosure: FDM-printed PETG, two-piece desktop shell with a screw-fastened bottom, edge-captured PCB, top openings for the four keycaps and display, LED light windows, and internal access to PROG. Please confirm these remaining choices:
  1. Is this a desktop/handheld indoor device?
  2. Should BAT1, BAT2, or both be externally accessible—and what battery dimensions must fit inside?
  3. Should the e-paper display be behind a clear protective window or directly exposed?
  4. Accept PETG with M2.5 screws, or specify your printer/material and preferred closure?
Once confirmed, I’ll generate the enclosure concept image for approval before creating the CAD model.
Desktop PETG enclosure
Protect display window
Internal battery option
Recommend battery bay
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Files

Schematic

Layout

Preview

IC1
BAT1
LED4
LED2
LED3
LED1
C4
Capacitance
10uF
R1
Resistance
150 Ω
R4
Resistance
150 Ω
C2
Capacitance
10uF
C6
Capacitance
1uF
R2
Resistance
150 Ω
C5
Capacitance
1uF
R3
Resistance
150 Ω
C1
Capacitance
0.1uF
C3
Capacitance
0.1uF
R5
Resistance
100kΩ
13
6
SW3
SW1
SW4
16
SW2
15
U3
U2
BUTTON_2
PROG
BAT2
IC1 Pin Description — ESP32-S3-WROOM-1-N4R8
IC1 is an Espressif ESP32-S3-WROOM-1-N4R8 module. It contains an ESP32-S3 SoC with integrated flash/PSRAM module resources and a PCB antenna. All digital GPIOs are 3.3 V domain unless otherwise constrained by the module variant and internal flash/PSRAM connections. Avoid applying voltages above 3.3 V to GPIOs.
Pin type legend from the Espressif module datasheet: P = power, I = input, O = output, T = high impedance/tri-state capable.
General usage notes
  • 3V3 power: Provide a stable 3.3 V rail with adequate bulk and local decoupling for Wi-Fi current bursts.
  • Grounding: Connect all GND pins and the exposed pad/center ground pads to the ground plane with short, low-impedance vias.
  • EN / CHIP_PU: Must not float. Use a pull-up to 3V3 and optional small capacitor to GND for reset noise immunity.
  • Strapping pins: GPIO0, GPIO3, GPIO45, and GPIO46 are sampled at reset. External circuitry must not force invalid boot states during reset.
  • Boot mode: For normal SPI flash boot, GPIO0 should be high at reset. Pull GPIO0 low during reset to enter download boot, with GPIO46 low or default.
  • USB pins: GPIO19 and GPIO20 are USB D−/D+ and are used by USB Serial/JTAG by default. Reusing them as GPIO disables that function.
  • JTAG pins: GPIO39–GPIO42 are JTAG-capable; avoid conflicting external loads if JTAG debugging is needed.
  • UART0 pins: TXD0/GPIO43 and RXD0/GPIO44 are the default serial console/programming UART pins.
  • Octal PSRAM restriction: This module is N4R8, so it includes 8 MB Octal PSRAM. ESPressif notes IO35, IO36, and IO37 are connected to Octal SPI PSRAM and are not available for other uses.
  • Antenna keepout: Keep copper, traces, components, and ground pour out of the module antenna keepout area per Espressif layout guidelines.
Pin-by-pin table

Table

Module pinSymbol pin name in projectTypePrimary / alternate functionsInput/output characteristicsSpecial considerations
1GND_1PGroundPower returnTie directly to ground plane.
23V3P3.3 V module supplyPower inputNeeds stable 3.3 V supply and decoupling; design for Wi-Fi burst current.
3ENIChip enable / reset inputHigh = module enabled; low = powered down/resetDo not leave floating. Pull up to 3V3; capacitor to GND can improve reset immunity.
4IO4I/O/TRTC_GPIO4, GPIO4, TOUCH4, ADC1_CH33.3 V bidirectional GPIO; RTC/touch/ADC capableGood general GPIO/ADC/touch pin. Avoid overvoltage; consider ADC source impedance.
5IO5I/O/TRTC_GPIO5, GPIO5, TOUCH5, ADC1_CH43.3 V bidirectional GPIO; RTC/touch/ADC capableGood general GPIO/ADC/touch pin.
6IO6I/O/TRTC_GPIO6, GPIO6, TOUCH6, ADC1_CH53.3 V bidirectional GPIO; RTC/touch/ADC capableGood general GPIO/ADC/touch pin.
7IO7I/O/TRTC_GPIO7, GPIO7, TOUCH7, ADC1_CH63.3 V bidirectional GPIO; RTC/touch/ADC capableGood general GPIO/ADC/touch pin.
8IO15I/O/TRTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P3.3 V GPIO; ADC2; UART0 RTS; optional 32 kHz crystal pinAvoid loading if using 32 kHz crystal function. ADC2 availability can be affected by firmware/peripheral use.
9IO16I/O/TRTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N3.3 V GPIO; ADC2; UART0 CTS; optional 32 kHz crystal pinAvoid loading if using 32 kHz crystal function.
10IO17I/O/TRTC_GPIO17, GPIO17, U1TXD, ADC2_CH63.3 V GPIO; UART1 TX; ADC2General GPIO/UART/ADC2.
11IO18I/O/TRTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, CLK_OUT33.3 V GPIO; UART1 RX; ADC2; clock outputGeneral GPIO/UART/ADC2; avoid unintended clock output conflicts.
12IO8I/O/TRTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7, SUBSPICS13.3 V GPIO; touch/ADC1; SPI alternateGood general GPIO/ADC/touch pin; can be SPI chip-select if configured.
13IO19I/O/TRTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D−3.3 V GPIO; USB D− capableReserved for USB Serial/JTAG or USB OTG if used; route as USB differential pair with IO20.
14IO20I/O/TRTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+3.3 V GPIO; USB D+ capableReserved for USB Serial/JTAG or USB OTG if used; route as USB differential pair with IO19.
15IO3I/O/TRTC_GPIO3, GPIO3, TOUCH3, ADC1_CH23.3 V GPIO; touch/ADC1Strapping pin for JTAG signal source. Avoid external circuits that force reset-time levels unintentionally.
16IO46I/O/TGPIO463.3 V GPIOStrapping pin. Default weak pull-down. Used with GPIO0 for boot mode and can control ROM message behavior; avoid pulling high/low incorrectly at reset.
17IO9I/O/TRTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD, SUBSPIHD3.3 V GPIO; touch/ADC1; SPI alternateGeneral GPIO; can conflict with SPI alternate functions if firmware config uses them.
18IO10I/O/TRTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4, SUBSPICS03.3 V GPIO; touch/ADC1; SPI alternateGeneral GPIO; SPI alternate available.
19IO11I/O/TRTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5, SUBSPID3.3 V GPIO; touch/ADC2; SPI alternateGeneral GPIO; ADC2 caveats apply.
20IO12I/O/TRTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6, SUBSPICLK3.3 V GPIO; touch/ADC2; SPI clock alternateGeneral GPIO; avoid loading if used as high-speed SPI clock.
21IO13I/O/TRTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7, SUBSPIQ3.3 V GPIO; touch/ADC2; SPI alternateGeneral GPIO; ADC2/SPI caveats apply.
22IO14I/O/TRTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS, SUBSPIWP3.3 V GPIO; touch/ADC2; SPI alternateGeneral GPIO; avoid conflict if used as SPI write-protect/DQS.
23IO21I/O/TRTC_GPIO21, GPIO213.3 V GPIO; RTC-capableGeneral GPIO; no ADC/touch listed.
24IO47I/O/TSPICLK_P_DIFF, GPIO47, SUBSPICLK_P_DIFF3.3 V GPIO on this N4R8 module; differential SPI clock alternateGeneral GPIO, but note special SPI differential clock alternate function.
25IO48I/O/TSPICLK_N_DIFF, GPIO48, SUBSPICLK_N_DIFF3.3 V GPIO on this N4R8 module; differential SPI clock alternateGeneral GPIO, but note special SPI differential clock alternate function.
26IO45I/O/TGPIO453.3 V GPIOStrapping pin. Default weak pull-down. For non-PSRAM/non-eFuse cases it can affect VDD_SPI voltage; avoid pulling high at reset unless intentional.
27IO0I/O/TRTC_GPIO0, GPIO03.3 V GPIO; RTC-capableBoot strapping pin. Default weak pull-up. Low at reset enters download boot; do not add large capacitance.
28IO35I/O/TSPIIO6, GPIO35, FSPID, SUBSPID3.3 V GPIO/SPI-capable in generic tableNot available for other use on ESP32-S3R8 / N4R8 modules because connected to Octal PSRAM.
29IO36I/O/TSPIIO7, GPIO36, FSPICLK, SUBSPICLK3.3 V GPIO/SPI-capable in generic tableNot available for other use on ESP32-S3R8 / N4R8 modules because connected to Octal PSRAM.
30IO37I/O/TSPIDQS, GPIO37, FSPIQ, SUBSPIQ3.3 V GPIO/SPI-capable in generic tableNot available for other use on ESP32-S3R8 / N4R8 modules because connected to Octal PSRAM.
31IO38I/O/TGPIO38, FSPIWP, SUBSPIWP3.3 V GPIO; SPI alternateUsable GPIO; can be SPI write-protect alternate.
32IO39I/O/TMTCK, GPIO39, CLK_OUT3, SUBSPICS13.3 V GPIO; JTAG MTCK; clock/SPI alternateAvoid loading/conflict if JTAG debugging is needed.
33IO40I/O/TMTDO, GPIO40, CLK_OUT23.3 V GPIO; JTAG MTDO; clock outputAvoid loading/conflict if JTAG debugging is needed.
34IO41I/O/TMTDI, GPIO41, CLK_OUT13.3 V GPIO; JTAG MTDI; clock outputAvoid loading/conflict if JTAG debugging is needed.
35IO42I/O/TMTMS, GPIO423.3 V GPIO; JTAG MTMSAvoid loading/conflict if JTAG debugging is needed.
36RXD0I/O/TU0RXD, GPIO44, CLK_OUT23.3 V GPIO; default UART0 RX inputUsed for serial bootloader/programming and console receive; keep accessible via programming header.
37TXD0I/O/TU0TXD, GPIO43, CLK_OUT13.3 V GPIO; default UART0 TX outputUsed for serial bootloader/programming and console transmit; keep accessible via programming header.
38IO2I/O/TRTC_GPIO2, GPIO2, TOUCH2, ADC1_CH13.3 V GPIO; touch/ADC1Good general GPIO/ADC/touch pin. In this project it appears connected to SW1.
39IO1I/O/TRTC_GPIO1, GPIO1, TOUCH1, ADC1_CH03.3 V GPIO; touch/ADC1Good general GPIO/ADC/touch pin.
40GND_2PGroundPower returnTie to ground plane.
41GND_3PExposed/center ground pad equivalentPower return and thermal/RF groundStitch to ground plane with vias.
42GND_4PGround padPower returnStitch to ground plane.
43GND_5PGround padPower returnStitch to ground plane.
44GND_6PGround padPower returnStitch to ground plane.
45GND_7PGround padPower returnStitch to ground plane.
46GND_8PGround padPower returnStitch to ground plane.
47GND_9PGround padPower returnStitch to ground plane.
48GND_10PGround padPower returnStitch to ground plane.
49GND_11PGround padPower returnStitch to ground plane.
IC1 connections observed in this project
  • 3V3 is connected to the main 3.3 V rail shared with U2, U3 output, capacitors, LEDs, and PROG pin 1.
  • EN is connected to R5 and PROG pin 6.
  • IO0 is connected to PROG pin 5 for boot/download control.
  • RXD0/TXD0 are connected to PROG pins 3/4 for programming UART.
  • IO9 is connected to U2 D/C.
  • IO12 is connected to U2 CLK.
  • IO2 is connected to SW1.
  • IO4 is connected through R4.
  • All listed GND pins are connected to the project GND net.
Sources
  • Espressif ESP32-S3-WROOM-1 / ESP32-S3-WROOM-1U Datasheet, Pin Definitions and Boot Configurations.
  • Espressif ESP32-S3 GPIO documentation and hardware design guideline notes for strapping pins.

  • General usage notes

  • Pin-by-pin table

  • IC1 connections observed in this project

  • Sources