Current Trace Width Analysis

3:39

Analyzing the PCB layout.

Analyzing the schematic.

Looking for "BQ24295 charge current limits, input current limits, system output current capability, battery current path, and any pin functions relevant to VIN, SYS, BAT, PMID, ISET, ILIM, TS, STAT, and OTG." in bq24295.pdf

Analyzing connector specifications.

Accessing knowledge base.

Looking for "What is the default fast charge current after reset, default minimum system voltage, default boost mode current capability, switching frequency, and any recommended external capacitor values for VBUS, PMID, BAT, SYS, REGN, and bootstrap?" in bq24295.pdf

Looking for "What is the current rating per contact and relevant PCB/layout current handling information for this JST B2B-PH-K-S(LF)(SN) connector?" in 1811151524_JST-Sales-America-B2B-PH-K-S-LF-SN_C131337.pdf

Calculating.

Estimating signal currents.

Calculating.

Looking for "What is REGN output voltage and the formula or default values for charge current programming, including whether fast charge current is set only by I2C on BQ24295?" in bq24295.pdf

I mapped the board’s current-carrying nets from the schematic and the charger’s datasheet-driven behavior, following the usual project-architecture and calculation workflow for this kind of analysis

Main assumptions

The layout is 2-layer.
I’m assuming 1 oz external copper.
The widths below are based on a conservative external-trace starting point and then rounded up for practicality.
The actual board is not a full 3 A implementation as drawn, because the JST PH connectors are only 2 A per contact and the input current is also limited by the ILIM network on R5.

What the board is intended to do

The core device U1 is a BQ24295 power-path single-cell Li-ion charger. From its datasheet:

Fast charge current capability: up to 3 A
Default fast charge current after reset: 1.024 A
SYS output capability: 3.5 A
Boost/OTG output capability on PMID: 1.5 A
Input current limit is the lower of the I2C setting and the ILIM pin setting

Also, the JST PH connectors used for VIN, BAT, SYS, and PMID are each rated 2 A per contact, so that becomes a practical board-level ceiling even where the IC could do more.

Derived current limits from this schematic 1. VIN / VBUS input net

The ILIM resistor R5 is 317 Ω.
From the datasheet relation for ILIM, that gives:

typical input limit: 1.37 A
datasheet spread: about 1.25 A to 1.50 A

So for the main VIN net, I would design around 1.5 A max.

2. BAT net

The battery net is on BAT+. In this design:

autonomous/default charging is 1.024 A
the IC can be programmed higher
but the battery connector is only 2 A

So:

default board behavior: about 1.0 A
practical max for this connectorized reference board: 2.0 A

3. SYS / VSYS net

This is the main system power rail. The IC can support more, but the SYS connector is also 2 A rated. So for this board I’d budget:

up to 2.0 A practical

4. PMID net

PMID is the power-path intermediate node and also the boost output node in OTG mode.

In boost mode, datasheet intent is 1.5 A
connector limit is 2 A

So the practical design current here is:

1.5 A

5. SW net

The SW node between U1, L1, and the bootstrap capacitor is the switching node. Its average current is tied to the power path, but its peak and AC ripple current are higher than the rail averages. This is the one net where width alone is not the main issue:

keep it short
keep the loop area tiny
use a fatter trace than the DC current alone suggests

Low-current control/signal nets

These do not need wide traces:

SCL, SDA, INT, OTG each have 10 kΩ pullups, so low-state current is only about 0.42 mA at 4.2 V
STAT LED path through R1 is about 1 mA order of magnitude
TS divider current is about 0.1 mA
ILIM pin current through R5 is about 3.15 mA
USB D+ / D- are signal nets, not current-carrying power nets

Recommended trace widths

Power nets for this board

Net	What it is	Current to design for	Minimum workable width	Recommended width
VIN / Net 6	Input from VIN/USB into charger	1.5 A	0.53 mm	0.8 mm
PMID / Net 2	Intermediate power node / boost output	1.5 A	0.53 mm	0.8 mm
BAT+	Battery charge/discharge path	1.0 A default, 2.0 A practical max	0.30 mm at 1 A, 0.78 mm at 2 A	0.8 mm
VSYS / Net 5	Main system rail	2.0 A practical	0.78 mm	1.0 mm
SW / Net 1	Switching node	treat as high pulsed current	0.8 mm	1.0 mm, very short
GND return for power path	Return for charger, inductor, caps, connectors	same class as power nets	not just a trace	solid pour preferred

Low-current nets

Net class	Typical current	Recommended width
SCL, SDA, INT, CE, OTG, TS, STAT	mA or sub-mA	0.15 to 0.20 mm
USB D+ / D-	signal only	0.15 to 0.20 mm minimum, matched routing matters more than current

My practical recommendation for this exact board

If you want one sane set of widths for the whole reference layout:

1.0 mm for VSYS, BAT+, and the main connector-to-power-path runs
0.8 mm for VIN and PMID
1.0 mm short trace/island for SW
0.20 mm for control nets
ground pour on both layers with lots of stitching vias around the charger power stage

Important caveat

If you truly want to use the BQ24295 near its 3 A charge capability, this board is not really dimensioned for that as shown:

connector current rating is only 2 A
2-layer compact layout makes thermal and current handling tougher
the power paths should get wider copper and ideally more copper area

So for the current design as drawn, I would treat it as roughly:

1.5 A input class
2 A system/battery connector class
1.5 A boost/PMID class

If you want, I can turn this into a net-by-net layout rule table for Flux, with explicit widths for:

Net 6 / VIN
Net 5 / VSYS
BAT+
Net 2 / PMID
Net 1 / SW
all remaining signal nets

27 days

ryanf

okay now make rulesets for each of those. be sure to use existing rulesets if they exist.

27 days

flux

0:33

Inspecting existing rulesets.

Analyzing the PCB layout.

Creating prompt for rulesets.

I can’t apply the rulesets directly in this project because you don’t have edit access here, but I checked the existing PCB rules and there are no existing per-net trace-width rulesets to reuse - only the default global rules plus cosmetic text overrides and a generic keep-out rule

Use this fork link to make an editable copy with the rules ready to add:

Fork project with trace-width rules

If you want, I can also give you the exact rule payloads/selectors to paste into an editable copy.

Give rule selectors

Add spacing too

Check DRC next

27 days

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Documents

Documents are markdown text files which describe project goals, capture details, or even simulation outputs.

Assets

BQ24295_image.png

BQ24295_imageThumbnail

Project Name

BQ24295 Reference Design

Description

This project is a reference design based on the BQ24295, a single cell Li-Ion battery charger. It manages the power between an external power source (VIN), a Li-Ion battery (BAT), and a system power rail (SYS). Key features include power-path management, battery thermistor monitoring, and charge status indication. #project #BQ24295 #ReferenceDesign #charger #BatteryManagement #referenceDesign #bms #texas-instruments #template #reference-design #polygon

Properties

License

creativecommons.org/licenses/by/4.0/

Pricing & Availability

Distributor	Qty 1
Digi-Key	$2.26–$4.80
LCSC	$8.55
Mouser	$7.58

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vasy_skral / BQ24295 Reference Design

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