Project Specification
Project Overview
Programmable 30–520 MHz RF band-pass filter using ADMV8052ACCZ and STM32H743VIT6, controlled over SPI with USB2 device and Cortex SWD.
Validated Interfaces
- RF: 50Ω SMA input/output with 10 nF DC blocks, optional DNP 0402 series/shunt matching footprints, and RF probe pads.
- SPI1 mapping is intentionally fixed: PB3=SCLK, PB4=MISO, PB5=MOSI, PA15=CS; PE11=SFL and PE10=ADMV reset.
- USB2 FS: PA11=DM, PA12=DP, PA9=VBUS sense; independent 5.1 kΩ CC1/CC2 Rd and USBLC6-2SC6 protection.
- SWD header: VTref, GND, SWDIO (PA13), SWCLK (PA14), and NRST only. SWO is intentionally omitted because PB3 is reserved for SPI1 SCLK. SWO/TDO and NC/TDI are explicit no-connects.
Power Input and Tree
J1 pinout: pin 1 +6V, pin 2 GND, pin 3 -6V.
- +6V_RAW → SS14 reverse-polarity diode → bulk/HF shunt → 2 A ferrite bead → +6V_FILT → LMR33630BDDAR 1.4 MHz buck → +3V3.
- +3V3 → ferrite bead → RF_3V3_FILT for ADMV8052 VDD.
- +3V3 → ferrite bead → +3V3_A for STM32 VDDA/VREF+.
- -6V_RAW → reverse-oriented SS14 → bulk/HF shunt → 200 mA ferrite bead → -6V_FILT → TPS7A3301RGW negative LDO → -2V5.
- ADMV8052 BYP is only the internal +2.5V bypass node and is not an external rail.
- Test points are provided on +6V_RAW, -6V_RAW, +3V3, -2V5, and GND.
Conservative Power Budget
Assumed high-performance profile: STM32H743 executing from internal memory at high clock/performance scale with USB FS active, SPI toggling at 10 MHz, two low-current LEDs, and no externally powered GPIO loads.
- STM32 representative high-performance current: 160 mA (datasheet all-peripherals-enabled representative value in the high-performance run-mode table).
- STM32 conservative datasheet maximum envelope: 750 mA at adverse temperature/conditions.
- ADMV8052: 0.135 mA static plus approximately fSCLK mA dynamic; use 10.2 mA at 10 MHz and budget 20 mA.
- USB/ESD/sensing and two LEDs: 10 mA budget.
- 3.3V representative total: about 190 mA.
- 3.3V worst-case design total: 780 mA; required with 25% margin: 975 mA.
- LMR33630 is rated 3 A, exceeding the required rail current by more than 3×.
- Negative rail: ADI evaluation guidance limits each external rail to 20 mA; design requirement with 25% margin is 25 mA. TPS7A3301 is rated 1 A.
Thermal and Headroom Checks
- A linear +6V-to-3.3V regulator was rejected: at 780 mA it would dissipate about 2.1 W, unsafe for a small LDO. The +3.3V rail therefore uses a switching buck.
- Positive headroom remains adequate after the SS14 drop: approximately 5.5–5.7V reaches the buck, well above 3.3V.
- TPS7A3301 worst planned dissipation is (6-2.5)V × 25mA = 87.5mW, safe in the exposed-pad VQFN with normal copper spreading. Negative-rail headroom is ample.
STM32 Support
- Five VDD pins each have a dedicated 100 nF capacitor; all VSS pins are grounded.
- Both VCAP pins have independent 2.2 uF low-ESR capacitors and are not connected to external rails.
- VDDA/VREF+ use a ferrite-isolated analog rail with 100 nF and 1 uF support; VBAT is tied to +3V3 with local bypass.
- BOOT0 has 10 kΩ pull-down. NRST has 10 kΩ pull-up and 100 nF to GND and is routed to SWD.
- Unused GPIO/LSE pins are explicitly marked no-connect.
Clock
Y1 is Abracon ABM8-25.000MHZ-B2-T3, 25 MHz, CL=18 pF, 50Ω max ESR, active and available from Mouser/Verical. With assumed total stray capacitance of 3 pF, equal load capacitors are C=2×(18-3)=30 pF. C25/C26 are 30 pF C0G/NP0 footprints.
RF Core
ADMV8052 VDD, VSS, BYP capacitor banks match the datasheet. All perimeter grounds and E1–E16 exposed pads are tied to GND. Optional DNP matching footprints and RF test pads are included at both ports.
Validation Status
Electrical Rule Check reports zero unresolved ERROR/WARNING/OPEN findings. The schematic is logically complete.
Sole Hard Blocker Before PCB Work
The current U1 library instance does not carry a usable exact CC-32-8 footprint: the generated footprint is approximately 1.6 mm square rather than the required 22 mm package. Flux project-level tools cannot replace a component-owned footprint with the exact asymmetric perimeter-pad geometry plus 4×4 exposed-pad array and segmented paste while preserving the schematic part. Figure 57 dimensions are recorded in Design Notes. Do not begin PCB placement/routing or manufacturing until an exact verified ADMV8052 CC-32-8 part footprint is authored in the backing part project and U1 is updated to that version.