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Project Specification
Status: Draft / blocked — do not proceed to PCB layout
Project Overview
Portable circular 70 mm Bluetooth loudspeaker electronics using a 3-series Li-ion pack, USB-C PD charging, protected high-current battery path, digital audio, and supervised user indication.
Intended Use
Production-intent compact battery-powered speaker for indoor/portable use. The PCB is expected to fit a circular 70 mm mechanical envelope; final outline, cell chemistry/capacity, acoustic enclosure, and thermal solution require mechanical validation.
What the Device Should Do
- Accept USB-C PD power and request 15 V, with 9 V and 5 V fallback profiles.
- Charge a 3S Li-ion pack at up to 3 A nominal with safe reduced limits where source/cell data are not final.
- Protect and pass at least 8 A continuous / 10 A peak on the battery power path.
- Receive Bluetooth audio through a certified QCC5125-based module and deliver I2S audio.
- Drive a floating 4 Ω speaker from an MA12070P in mono/PBTL at 30 W continuous and 45 W peak target.
- Supervise charge, PD presence, mute, battery voltage, button, and indicators with an ATtiny1616.
Main Features
- Reinforced USB-C receptacle; CC/VBUS ESD and surge protection; controlled inrush.
- Autonomous 3–5S BMS with back-to-back MOSFETs, shunt, fuse strategy, NTC support, and passive balancing.
- Efficient 3.3 V auxiliary rail; common GND with filtered digital/audio domains.
- IP67 external button interface, RGB indication, UPDI and critical I2C debug pads.
- External interfaces for speaker, B-/B1/B2/B+, protected PACK+/PACK-, NTC, optional TRRS, and optional passive-radiator sensor pads.
System Architecture
Diagram
Hardware Subsystems
USB-C PD
STUSB4500 preferred. Integrated sink Rd means no external CC pull-down resistors. Configure PDOs for 15 V preferred and 9 V/5 V fallback. Use documented VBUS discharge/inrush/protection network.
Current implementation uses TPD6S300RUKR between the receptacle and STUSB4500 CC pins for USB-PD short-to-VBUS/ESD protection, including 1 µF VPWR and 100 nF/50 V VBIAS support. PESD18VF1BLS-QYL protects the 15 V VBUS domain. PDO intent remains 15 V preferred with 9 V/5 V fallback; final STUSB4500 NVM programming and production verification are still required.
VBUS is now split into
USB_VBUS_PROTECTED upstream and CHARGER_VBUS downstream. U_PD:VBUS_EN_SNK (high-voltage open-drain, active by pulling low) controls a default-off external switch formed by back-to-back Q_PD1/Q_PD2 DMP3013SFV P-channel MOSFETs. R_PD_GS = 100 kΩ holds the common gate at the common-source node while the output is Hi-Z; R_PD_GATE = 1 kΩ limits gate drive and C_PD_GATE = 100 nF controls turn-on/inrush, following the ST application values. Each MOSFET is rated 30 V and 12 A (17 mΩ maximum at VGS = -4.5 V), providing margin over 15 V / 3 A; the opposed pair prevents charger-side backfeed. U_PD:VDD, U_PD:VBUS_VS_DISCH through 470 Ω, the connector, and the VBUS TVS remain upstream. All BQ25798 VBUS/VAC inputs and input capacitors are downstream, with no direct bypass around the switch.Charger / Power Path
BQ25798/BQ25792 preferred, 1–4S buck-boost, 5–15 V input, 3 A nominal charge. Implement the exact selected-device reference network: inductor, input/output/REGN capacitors, bootstrap, ILIM, TS/NTC, sense elements, and I2C. Cell-dependent charge voltage/current and TS network values remain provisional until the exact cell pack is approved.
Battery / BMS
3S cell connector exposes B-, B1, B2, B+. Protected output is PACK+/PACK-, with XT30 on the protected high-current path. Use an autonomous 3–5S protector in the BQ77915 family or documented equivalent, back-to-back N-MOSFETs, current shunt, fuse, two temperature inputs where supported, and passive balancing.
Auxiliary Rails
Generate 3V3_DIG from PACK_PROTECTED/VSYS using a buck rated for at least 15 V input and at least 1 A peak. Derive 3V3_AUDIO through ferrite filtering if supported by the selected module/amplifier control domain. GND remains common. Add 1.8 V only if the selected Bluetooth module requires it.
Bluetooth / DSP
Use only a commercially certified QCC5125 module with integrated antenna and publicly verifiable pinout. Respect antenna edge placement and keepout. If no suitable library module/pinout is available, expose documented interface portals/connectors and leave this block explicitly open—do not invent module pins. Optional TRRS is DNP unless analog-input compatibility is verified.
No qualified QCC5125 module was found. J_QCC_IF is a provisional board-side interface carrying 3V3, GND, I2S BCLK/LRCLK/data, I2C, RESET, ENABLE and GPIO. Its numbering is not a QCC module pin map and must not be treated as one.
Amplifier
Infineon MA12070P, mono/PBTL, powered from protected battery/VSYS. Implement datasheet decoupling, charge-pump/bootstrap, I2C/address/mute/reset, and a differential LC output network for 4 Ω. Output inductors require Isat ≥5 A and low DCR; bulk/filter capacitors ≥25 V. Neither speaker terminal connects to GND.
Supervisor / UI
ATtiny1616 at 3.3 V. Measure protected pack through a high-impedance divider, RC filtering, and input protection so ADC remains below VDD at 12.6 V and fault conditions. Prefer charger/BMS telemetry rather than direct cell-tap ADC wiring. Provide UPDI, I2C debug pads, external protected/debounced button, RGB indicator, and signals CHARGE_STATUS, PD_PRESENT, AMP_MUTE, BATTERY_LOW.
Interfaces and Connections
Table
| Interface | Signals / requirement |
|---|---|
| USB-C | VBUS, CC1, CC2, shield; PD sink only |
| Cell pack | B-, B1, B2, B+ mandatory |
| Protected power | PACK+, PACK-; XT30 rated ≥10 A peak |
| Speaker | SPK_OUT_P, SPK_OUT_N, floating, connector ≥5 A |
| Digital audio | I2S BCLK, LRCLK/FS, BT SDOUT→AMP SDIN; MCLK only if required |
| Control | Common 3.3 V I2C, reset/enable/mute/status |
| Programming | UPDI + GND + 3V3 reference pads |
| UI | IP67 button connector/pads, RGB LED connector or on-board LED |
| Thermal | Pack NTC interfaces; charger TS as documented |
| Optional | TRRS DNP pending module pinout; passive-radiator sensor pads |
Power and Runtime Expectations
Battery range 9.0–12.6 V. Audio target is 30 W continuous / 45 W peak. Runtime depends on final cell capacity, listening crest factor, and thermal limits; no runtime claim is made before the cell selection.
Power Tree and Power Budget
See the durable Power Budget file. The entire battery path is sized for ≥8 A continuous / 10 A peak. Speaker output/filter/connector path is sized for ≥5 A.
Manufacturing and Assembly Expectations
Professional SMD assembly. Real orderable components with verified symbols/footprints are required. Power MOSFETs, shunts, connectors, inductors, and copper must be thermally/current rated. Final PCB requires antenna keepout, high-current copper and via analysis, and mechanical confirmation within 70 mm.
Firmware-Relevant Hardware Requirements
- UPDI programming access.
- I2C access to charger and amplifier; optional BMS telemetry only if supported.
- ADC protected-pack measurement using internal reference where appropriate.
- Debounced button input; RGB PWM outputs; PD/charge status inputs; amplifier mute output.
- Safe boot defaults: amplifier muted, charging in conservative mode until configured.
U_MCUpins PB1, EXTCLK/PA3, PC0, PC1, PC2, and PC3 are reserved and explicitly No Connect in this revision. Firmware must configure them to a defined safe state (for example output-low or input with an enabled internal pull resistor, as appropriate) so they do not remain floating.
Physical Design Expectations
Circular 70 mm target envelope. USB-C, speaker, battery, button, and indicator interfaces must align with enclosure openings. Integrated Bluetooth antenna must face the board/enclosure edge with copper/component keepout per module documentation. Keep high-current switching loops and class-D outputs away from RF and ADC sensing.
Important Design Decisions
- Passive—not active—cell balancing is selected for safety, area, verification burden, and complexity.
- Common GND is retained; noise domains are separated through filtering and placement, not isolated ground planes.
- Bluetooth uses a certified module, not bare QCC5125 silicon.
- Speaker output is fully differential/floating.
- Cell-tap connector is mandatory; XT30 alone is not adequate for BMS access.
- The charger VBUS is isolated from connector-side protected VBUS and is enabled only by
U_PD:VBUS_EN_SNKthrough the external default-off, slew-controlled, reverse-blocking 30 V / ≥3 A switch stage. - The library symbol may classify
VBUS_EN_SNKas a power input and therefore produce an ERC false positive. Electrically it is the STUSB4500 high-voltage open-drain control output; the required functional connection toR_PD_GATEmust be retained.
Assumptions / Open Items
- Final cell chemistry, capacity, approved charge current, thermistor curve, connector family, and pack fuse are pending.
- 30 W continuous may be thermally difficult in a sealed 70 mm product; validate enclosure, heatsinking, and acoustic load.
- Bluetooth module remains open if no publicly documented certified QCC5125 module is available in the library.
- Final PD sink NVM profile programming method and production test flow are pending.
- The BQ25798, BQ7791502 and MA12070P support networks are not complete in the present schematic revision; layout is explicitly blocked until their reference circuits and ERC are completed and independently reviewed.
- The current four-contact cell connector footprint does not provide four independent electrical contacts suitable for B-/B1/B2/B+ and must be replaced before layout.
Acceptance Criteria
- Functionally wired, readable block-organized schematic with named inter-block nets.
- Every active wired from datasheet evidence; one decoupler per supply pin plus domain bulk.
- Real components with verified symbols/footprints; all intentional unused pins marked NC.
- ERC/design review has no unresolved real errors; any remaining warnings are documented.
Change Notes
- Initial architecture captured from the user brief.
- Passive balancing formally replaces the earlier active-balancing request.
- Provisional electrical sizing captured pending final cell and module choices.
- Added USB-PD CC short-to-VBUS protection, 15 V VBUS TVS, UPDI, external button debounce, RGB connector/current limiting, and a provisional QCC5125 board-side interface.
- Added the STUSB4500-controlled external VBUS isolation switch, split upstream/downstream VBUS nets, and reserved six unused ATTINY1616 GPIOs as explicit No Connects.
- Recorded that the design is not ready for layout because charger, BMS and amplifier completion remains open.
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
USB-C PD
Charger / Power Path
Battery / BMS
Auxiliary Rails
Bluetooth / DSP
Amplifier
Supervisor / UI
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Firmware-Relevant Hardware Requirements
Physical Design Expectations
Important Design Decisions
Assumptions / Open Items
Acceptance Criteria
Change Notes
