Building a Locker Control Board

Thought for 11 sec

I’ll treat each lock as a 4-wire 24 V device: two coil wires plus two 24 V lock-state wires. I’ll add 16 protected 24 V-tolerant state inputs using input shift registers, update the connectors/interface docs, and verify the schematic changes.

Worked for 2 mins 10 sec

flux

I’m adding isolated 12/24 V state sensing: each state wire drives an optocoupler input, and two 74HC165 input shift registers report the 16 states to the ESP32-S3.

Worked for 10 mins 46 sec

flux

Updated the design for 4-wire 12/24 V locks: each lock now has coil drive plus isolated 12/24 V state sensing, read through two 74HC165 input shift registers. I also updated the project specification, firmware starter, bring-up plan, and FMEA; validation now shows only expected unused ESP32 dev-board pin warnings.

Estimated time saved vs. manual EDA workflow: ~4–6 hours.

Open items:

Confirm state polarity: whether the 24 V state signal means “locked” or “unlocked.”
Confirm real lock coil current and max simultaneous activations.
Finalize the buck regulator values before PCB layout.

Suggested next steps:

Define the exact connector pinout labeling/silkscreen.
Finalize U2 regulator passives from the datasheet.
Place the 16 lock connectors and high-current driver section on the PCB.
Add firmware CAN command handling and state reporting.

Label, finalize, layout

Add connector labels

Finalize regulator

Start PCB placement

Check BOM cost

Files

Schematic

Layout

Preview

J11

J16

J18

J14

J12

J17

J13

J15

Project Specification — Multi-Lock Controller

Purpose

Functionally similar electronic lock controller inspired by the photographed locker check board, implemented as a clean new design rather than a clone.

Current Architecture

12/24 V DC lock supply input through terminal block, fuse, TVS, and bulk capacitance.
3.3 V logic rail generated from the lock supply using LMR33630 buck-regulator block.
ESP32-S3 DevKitC main controller for USB programming, control firmware, test mode, CAN/TWAI, lock drive, and lock-state scanning.
Two SN74HC595 shift registers provide 16 lock-control outputs.
Sixteen low-side N-MOSFET channels switch 12/24 V locks/solenoids.
Each output channel includes a gate resistor, gate pulldown, flyback diode, and dedicated 4-wire lock connector.
Each lock connector is now intended as: pin 1 = +12/24 V coil supply, pin 2 = switched coil return, pin 3 = 12/24 V state+, pin 4 = state-.
Sixteen optocouplers isolate the 12/24 V lock-state signals from 3.3 V logic.
Two 74HC165 parallel-in/serial-out shift registers report the 16 isolated lock-state bits to the ESP32-S3.
CAN transceiver and 2-pin CAN connector are included.
8-position DIP switch provides active-low configuration inputs.

Assumptions

Locks may be 12 V or 24 V, but the controller power input and state input conditioning are designed around 24 V-tolerant operation.
Output count: 16 lock/solenoid channels.
Lock outputs are low-side switched; external locks connect between +12/24 V and the switched return.
Lock state output is treated as a 12/24 V signal that drives an optocoupler input.
Simultaneous lock activation must be limited in firmware unless the power supply, fuse, connectors, and copper are upsized.

Important Open Engineering Items

Regulator passives are still preliminary; the LMR33630 feedback network, BOOT capacitor, VCC capacitor, compensation/PG handling, and inductor/current ratings need datasheet-final verification before PCB layout.
Actual lock current is unknown; MOSFET thermal design, fuse rating, connector current rating, and trace width must be adjusted once lock current and simultaneity are defined.
Confirm whether the lock-state wires are polarity-sensitive and whether state asserted means locked or unlocked.
CAN termination should be made selectable if this board may be used in the middle of a CAN bus.
Final PCB layout needs high-current copper pours and separated logic/power-current routing.

Purpose
Current Architecture
Assumptions
Important Open Engineering Items