ESP32 S3 Circuit Design
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Work done
- Assessed the existing Ethernet block and confirmed the previous RMII PHY architecture centered on U3 was the non-viable portion to replace.
- Researched an ESP32-S3-compatible LAN approach and selected a W5500 SPI Ethernet controller as the safer replacement architecture.
- Replaced the old LAN PHY block in the schematic: removed the prior LAN8720A-CP-based support parts and added a new U3 plus new support parts C6, C7, R7, R8, R9, and R14.
- Preserved the existing integrated-magnetics RJ45 connector J2 for DIN-rail mechanical continuity.
- Verified the pre-replacement schematic had no critical ERC findings before the swap.
Success criteria review
- ✅ The non-viable Ethernet architecture was identified and the replacement direction was implemented in the schematic.
- ✅ A LAN solution proven compatible with the ESP32-S3 was selected: SPI Ethernet via U3.
- ✅ The DIN-rail connector strategy was preserved by keeping J2 in place.
- ❌ The new LAN interface is not yet fully wired. After component replacement, the old net connections were destroyed and the new U3 still needs full SPI, power, reset/interrupt, PMODE, and magnetics-side rewiring.
- ❌ The project is not yet ready for layout review, because the new Ethernet block still needs connectivity restoration and then ERC/DRC re-validation.
3 days
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Design Notes
System architecture
- Form factor: DIN rail enclosure T2, 36 mm width.
- Board target size: 36 mm x 95 mm rectangular layout with 2 mm corner radius.
- Mains input: 230 VAC via top terminal block.
- Internal low-voltage rail: isolated 5 V from AC/DC converter module.
- Controller: ESP32-S3 module for Wi-Fi plus application control.
- Additional 802.15.4 radio: ESP32-H2 companion module for Zigbee, Thread, and Matter over Thread support.
- Ethernet: LAN8720A PHY plus integrated-magnetics RJ45 connector.
- USB-C: one bottom edge connector for ESP32-S3 service and one dedicated USB-C connector for ESP32-H2 flashing.
- LED interface: central terminal block on the low-voltage side.
Key engineering decisions
- Use an isolated AC/DC module for 230 VAC to 5 V conversion to maintain mains safety boundaries and simplify DIN-rail implementation.
- Use an ESP32-S3 module instead of bare silicon to improve RF implementation and certification readiness.
- Add a dedicated IEEE 802.15.4 companion module because ESP32-S3 alone does not provide native 802.15.4.
- Use a 4-layer layout because the design includes mains isolation, RF, Ethernet, USB, and mixed-voltage digital routing.
- Place AC input at the top, LED terminal in the middle, and USB-C plus RJ45 on the bottom side to align with requested field wiring orientation.
- Keep the original USB-C port on ESP32-S3 and add a second dedicated USB-C programming path for ESP32-H2 to avoid shared-programming ambiguity.
ESP32-H2 flashing assessment
- The existing USB-C connector J3 is wired directly to U1 native USB on IO19/IO20.
- U2 is connected to U1 only through UART0 using R5 and R6.
- The original design did not expose a dedicated USB data path to U2 and did not provide an explicit H2 download-mode hardware path separate from the main controller.
- ESP32-H2 datasheet facts used for the decision:
- native USB Serial/JTAG is available on IO26 = USB_D- and IO27 = USB_D+
- UART0 is available on RXD0/TXD0
- Joint Download Boot requires GPIO8 = HIGH and GPIO9 = LOW during reset sampling
- Conclusion: U2 was not reliably or efficiently flashable through the original J3 service connector without additional control logic and firmware cooperation from U1.
Dedicated H2 programming interface
- Added J5 as a dedicated USB-C receptacle for U2 firmware flashing.
- Added D2 as USB ESD protection for the new H2 USB port.
- Added R10 and R11 as 5.1k CC pull-down resistors for the new USB-C port.
- Added C11 as local VBUS bypass on the new programming connector.
- Wired the new port directly to U2 native USB:
- Added R12 and R13 to bias H2 boot strap nets:
- H2_BOOT_GPIO8 pulled HIGH
- H2_BOOT_GPIO9 pulled LOW
- This dedicated interface separates H2 flashing from S3 service access and avoids contention on the inter-processor UART link.
Schematic partitioning
- AC mains block: J1, F1, RV1, PS1.
- 5 V and 3.3 V power block: C1, C2, U4, C3, C4, C8, FB1.
- Main controller block: U1 with decoupling and boot/enable resistors.
- 802.15.4 companion block: U2 with UART link to U1 and a dedicated USB flashing port.
- Ethernet block: U3, Y1, C9, C10, R7, J2, R8, R9.
- USB service block for S3: J3, R1, R2, D1.
- USB flashing block for H2: J5, D2, R10, R11, R12, R13, C11.
- LED field I/O block: J4.
Layout guidance
- Keep the entire mains block at the top edge with clear isolation from the low-voltage domain.
- Keep the LED connector near the board center for harness accessibility.
- Keep the USB-C connectors on the bottom edge.
- Keep the RJ45 connector on a board edge in the lower half of the layout.
- Keep RF modules away from the AC/DC module and away from the RJ45 shield region as much as possible.
- Keep the PHY crystal and load capacitors tightly clustered around U3.
- Keep USB ESD protection directly adjacent to J3 and J5.
- Place J5 so the DIN-rail front access remains within the 36 mm enclosure width; use the board length direction for connector spacing rather than increasing width.
Open items for follow-up
- Add explicit mains creepage documentation and safety review.
- Improve Ethernet strap and reset details if PHY bring-up testing requires refinements.
- Decide whether the LED connector should expose only data+ground or data+power+ground in a later revision.
- If completely automatic H2 boot entry is desired from a host PC without manual intervention, add a reset/download gating circuit for EN and strap control in a later revision.
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