flowchart TD subgraph HV [High Voltage Section] J1[Mains Connector\nBLK, WH, GRN] Fuse[Fuses & MOV] T1[PCB Transformer\n120VAC->24VAC] J3[Motor Connector\nWHT, BLK, PE] end subgraph Barrier [Isolation Barrier] T1 --> BR1[Bridge Rectifier] end subgraph LV [Low Voltage Control Section] DC24[24VDC Supply] Timer1[150 ms On-Delay Timer 1] Timer2[150 ms On-Delay Timer 2] K1[DPDT Relay\nForward] K2[DPDT Relay\nReverse] J2[Pendant Connector\nFWD, NEU, REV] end J1 --> Fuse --> T1 BR1 --> DC24 DC24 --> Timer1 DC24 --> Timer2 Timer1 --> K1 Timer2 --> K2 K1 --> J3 K2 --> J3 J2 --> Timer1 J2 --> Timer2

Four corner keepout zones around each mounting hole for mechanical clearance and safety separation

Industrial/Manufacturing

No explicit layout rule violations are currently reported by Flux’s live DRC for this project. However, the tool does not expose individual "ghost" outline artifacts as DRC errors, so visually invisible or unclickable silkscreen/outline remnants (like the KS outline, extra J2, and duplicate D1 outlines mentioned in review) will not show up here and must be cleaned manually in the PCB editor.

LINE, NEUTRAL, MT1, GATE

All standard checks (airwires, floating copper, overlapping copper/fills, invalid layers, missing footprints, deprecated rules, trace corner radius, protected intrusions) are passing based on the latest review snapshot.

Mains

FWD, REV, GND

Switches