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Design Requirements and Power Budget
Architecture
- Raspberry Pi Pico module (RP2040), powered from reader/card +5 V through VSYS.
- External connector mapping: 1 +5V/card VCC, 2 RESET, 3 CLOCK, 4 DATA, 5 AUX1, 6 AUX2, 7 VPP, 8 GND.
- GPIO mapping: GP2 CLK_SENSE, GP3 RST_SENSE, GP4 DATA_SENSE, GP5 DATA_DRIVE_LOW.
- CLK/RST/DATA sense use 10 kΩ upper and 20 kΩ lower dividers (5 V to approximately 3.33 V).
- DATA is pulled up to card +5 V with 4.7 kΩ and may only be actively pulled low through a 5 V-tolerant open-drain stage.
Performance
- Input paths must retain several-hundred-kilohertz electrical margin. Do not add shunt filter capacitors; use low-capacitance ESD protection so divider/GPIO capacitance does not materially slow edges.
- Firmware requirement: use RP2040 PIO, default to standards-compliant 50 kHz, and expose a configurable higher-frequency test mode. CPU edge-interrupt timing is not acceptable.
Preliminary Power Budget
The Pico module is the dominant load. A conservative design allowance of 150 mA peak at VSYS plus under 5 mA for the interface buffer and divider/pull-up currents remains well below the Pico onboard regulator/input-path capability and a standard 2.54 mm connector contact rating. No external regulator is added.
- DATA pull-up worst case when low: 5 V / 4.7 kΩ = 1.06 mA.
- Each 10 kΩ + 20 kΩ divider at 5 V: 0.167 mA; three dividers total 0.50 mA.
- Logic buffer supply: low-mA allowance, with local 100 nF bypass.
- Design input allowance: approximately 160 mA peak from reader +5 V.
USB Coexistence
The Pico VSYS input is used as intended. The Pico module's onboard USB/VSYS power arrangement prevents direct USB VBUS-to-reader backfeed in the normal configuration; do not externally tie reader +5 V to Pico VBUS. If USB is connected while reader +5 V is present, both sources must remain within Pico documentation limits.
Architecture
Performance
Preliminary Power Budget
USB Coexistence
