This session established the actual release state and completed the crystal correction, but the board is not yet fab-ready.
Independent audit confirmed the original USB route has four asymmetric through-vias, approximately 3.4 mm skew, variable geometry, and loose coupling. A fabrication impedance note cannot make that production-safe.
The 32.768 kHz crystal block was rebuilt successfully: X1/C15/C16 placement and XL1/XL2 are now short, local, Top-only, and via-free.
The USB rebuild exposed a D+/D− pin-order crossover between J1, U7, and U1. Reorienting U7 and restoring the displaced routes was launched, but I could not retrieve and independently reconcile its final report.
The last confirmed intermediate state was commit #7214da2f with 13 airwires, so manufacturing exports were correctly withheld.
BOM consolidation/mapping issues also still require correction before PCBA release.
Remaining release work:
Confirm the latest live routing state and restore any remaining airwires.
Complete USB as a Top-only, via-free, consistently coupled pair with ≤0.5 mm skew.
Correct BOM grouping and remaining LCSC mappings.
Run fresh independent ERC, DRC, route-layer, RF, footprint, and assembly audits.
Generate and inspect Gerber/drill, BOM, and pick-and-place files.
Assembly source: LCSC C2843335, JLCPCB extended part
Package / footprint:USON-8 EP, 2.0 × 3.0 mm, 0.50 mm pitch; Flux package code USON-8_L3.0-W2.0-P0.50-BL-EP
Supply: 3V3
Local decoupling: C14, 100 nF ceramic, 0402, 10 V
Chip-select pull-up: R9, 10 kΩ, 0402, 1%, from QSPI_CS to 3V3
IO2/IO3 pull-ups: not fitted. The selected IQ ordering has Quad Enable factory-fixed high; the datasheet recommends an optional /CS pull-up and does not require external IO2/IO3 pull-ups for this ordering.
Exposed pad: connected to GND as a conservative board-level thermal/mechanical convention. The available UX-package datasheet does not explicitly state an EP electrical requirement, so this remains a documented implementation assumption.
GPIO Mapping
Table
QSPI signal
U1 module pin
nRF52840 GPIO
U9 pin
QSPI_CS
P12
P0.12
/CS (pin 1)
QSPI_CLK
P17
P0.17
CLK (pin 6)
QSPI_IO0
AI2
P0.04
DI/IO0 (pin 5)
QSPI_IO1
AI3
P0.05
DO/IO1 (pin 2)
QSPI_IO2
P15
P0.15
WP#/IO2 (pin 3)
QSPI_IO3
P0.22
P0.22
HOLD#/RESET#/IO3 (pin 7)
The six GPIOs were previously unused, exposed on the E73 module, and are outside the nRF52840 low-frequency-only GPIO set.
PCB Placement and Routing Status
U9, C14, and R9 are placed on the Bottom side above-left of U1, outside the BLE antenna end/edge region.
Final centers: U9 (7.5, -4.0) mm, C14 (9.5, -2.9) mm, R9 (5.5, -2.9) mm.
Placement checks: no component overlap, no keepout violation, and no out-of-bounds component.
Valid surgical routing preserved:
U9 /CS to R9 P1 on QSPI_CS
U9 VCC to C14 P1 on 3V3
R9 P2 to the local 3V3 cluster
Whole-board autorouting was not run.
Two attempted QSPI_CLK routes were removed because the deterministic layer transition created stacked/multiple-via copper-overlap errors. No invalid CLK route was retained.
Verification Snapshot
ERC
Completed — clean. Fresh electrical checks reported no open errors or warnings, including floating pins, no-connect misuse, driver conflicts, undriven nets, single-pin nets, and power-pin checks.
DRC
Partially completed. Fresh selected DRC checks reported only seven airwire errors; no overlapping-copper, overlapping-trace, component-body-overlap, keepout, board-edge, out-of-bounds, missing-footprint, dangling-trace, invalid-layer, or stackup errors were returned.
Residual airwires — 7
QSPI_CS: U1 P12 ↔ U9 /CS local cluster
QSPI_CLK: U1 P17 ↔ U9 CLK
QSPI_IO0: U1 AI2 ↔ U9 DI/IO0
QSPI_IO1: U1 AI3 ↔ U9 DO/IO1
QSPI_IO2: U1 P15 ↔ U9 WP#/IO2
QSPI_IO3: U1 P0.22 ↔ U9 HOLD#/RESET#/IO3
Local flash 3V3 cluster ↔ existing board 3V3 routing
Routing state reports zero dangling traces.
Router preflight residual
A pre-existing warning remains on U6: two overlapping microphone GND pads are on the same GND net and are treated as one pin by the router. This is unrelated to U9.
Scope Status
Completed: part selection, exact footprint selection, GPIO assignment, schematic wiring, support passives, net naming/classification, valid PCB placement, local CS/power routing, fresh ERC, fresh DRC, and routing-state inspection.
Failed: full surgical completion of the six U1-to-U9 QSPI routes; attempted CLK routing produced invalid multi-via overlaps and was rolled back.
Unattempted by instruction: whole-board autoroute.