EEG System PCB Design Guide
Thought
Work done
- Looked up library parts for the key ICs/connectors: ADS1299IPAGR, ESP32-S3-MINI-1U-N8, CP2102N-A02-GQFN28, USB-C receptacle (example: 105455-0101), and the mezzanine connector DF40C-60DS-0.4V(51).
- Retrieved the required internal execution checklists for schematic/layout/constraints so the next edits follow Flux procedure .
Success criteria review
- ❌ Two separate Flux projects were not created (I only have access to the single current project context).
- ❌ Analog + digital schematics were not yet built (no components/nets placed/wired).
- ❌ DF40 interleaved-GND pin map not yet instantiated/documented in-project.
- ❌ 4-layer stackup + layout rules not yet configured.
Next steps
- Please create (or share links to) two empty Flux projects named EEG Analog and EEG Digital, or confirm you want me to proceed inside this single project first (and later duplicate/split).
- Once you confirm, I will: (1) set each project description, (2) add the DF40 connector(s) and define the pin map, (3) add/place the required ICs, passives, and protection parts, (4) wire shared SPI with per-AFE CS/DRDY plus shared START/RESET, and (5) set 4-layer stackup + initial layout rules, then check ERC/DRC.
No schematic yet
Talk to Flux to get started.
