Supercapacitor Power Module Design

flux

Work done
  • Reconciled the project plan to the locked KiCad v0.4 FDfence architecture and preserved the authoritative constraints in Design Notes.
  • Confirmed the locked bottom-board topology around C1 through C6, the top-board continuation through C7 to C9, passive balancing on R1 to R6, duplicated charging terminals TERM1_FRONT to TERM4_FRONT, bus bridges STND_PLUS and STND_MINUS, and the dual-purpose ROD1 on N_C6_TOP.
  • Verified the locked capacitor target is Vishay BCcomponents MAL223551006E3 and that the uploaded KiCad symbol library references footprint FDfence:EDLC_MAL223551006E3.
  • Identified the remaining implementation deltas still needed in the live project: C1 to C9 still need the final part assignment, R1 to R6 still need 1206 PCB footprints, TERM1_FRONT to TERM4_FRONT, STND_PLUS, STND_MINUS, and ROD1 still need the locked geometry, and the bottom layout still needs the exact trefoil outline, final placement, copper rules, and DRC cleanup.
Success criteria review
  • ✅ Locked requirements are fully captured and internally consistent with the KiCad v0.4 reference.
  • ✅ The remaining migration steps are clearly defined and ready to execute.
  • ❌ I could not apply the remaining schematic or PCB write operations in this session.
  • ❌ The project is not yet restored to full conformance with the locked KiCad v0.4 design.
Next steps I’m blocked because project write operations are unavailable in this session. When execution is available again, the next pass should finish the real edits in order: assign MAL223551006E3 to C1 through C9, correct R1 through R6 to 1206 on the PCB, swap the terminal/standoff/rod geometry to the locked dimensions, remove top-board-only population from the bottom layout, and then proceed with PCB layout completion: exact trefoil outline, locked placement, solid no-thermal high-current rules, routing cleanup, DRC, and final BOM validation.

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Design Notes
Locked Architecture
  • The project follows the locked KiCad v0.4-derived 9S supercapacitor pack architecture.
  • Use a 9-cell series supercapacitor stack based on Vishay BCcomponents 235 EDLC-HVR ENYCAP parts.
  • The locked capacitor MPN is MAL223551006E3.
  • The design uses passive balancing, not active balancing.
  • The design assumes no potting.
Locked Capacitor Specification
  • Manufacturer Name: Vishay BCcomponents
  • Manufacturer Part Number: MAL223551006E3
  • Family: 235 EDLC-HVR ENYCAP
  • Capacitance: 25F
  • Operating Voltage: 3.0V nominal class; rated up to 2.6V at 85C
  • Mechanical envelope: 16 mm diameter x 25 mm length
  • Ruggedization note: use the 85C / 85% RH chemistry version
Bottom Board Topology
  • The pasted KiCad v0.4 bottom-board file is the electrical and mechanical source of truth for the lower board.
  • Board title reference: FDfence Capacitor PCB - Bottom Board (6S).
  • Construction target: 2-layer FR4, 2 oz copper, ENIG.
  • Lower-board series order is locked as: C1 -> C4 -> C2 -> C5 -> C3 -> C6 -> top-board handoff.
  • The top-board handoff occurs through the central rod on net N_C6_TOP.
  • The complete 9S electrical chain is PACK_PLUS -> C1 -> C4 -> C2 -> C5 -> C3 -> C6 -> N_C6_TOP -> C7 -> C8 -> C9 -> PACK_MINUS.
Bottom Board Mechanical Reference
  • The lower board uses the custom trefoil outline defined by the KiCad v0.4 Edge.Cuts geometry.
  • A central rod feature is present at the board origin.
  • Standoff bus bridges are located at (-12 mm, -12 mm) and (12 mm, -12 mm).
  • The lower board includes six radial EDLC footprints arranged exactly at the KiCad coordinates.
  • The current locked architecture does not use potting-flow cutouts.
Components and Interfaces
  • Bottom-board supercapacitors: C1, C4, C2, C5, C3, C6.
  • Upper continuation supercapacitors: C7, C8, C9.
  • Balancing method: one passive resistor across each lower-board cell segment.
  • Balancing resistors R1 through R6 are locked to 1kΩ, 1%, 0.25W, 1206 SMD.
  • TERM1_FRONT and TERM2_FRONT are the duplicated positive front charging terminals tied directly to PACK_PLUS.
  • TERM3_FRONT and TERM4_FRONT are the duplicated negative front charging terminals tied directly to PACK_MINUS.
  • The front terminal duplication is required so the docking station 12A current is split across two pogo contacts per polarity.
  • STND_PLUS carries global PACK_PLUS from the bottom board to the top board through a brass standoff.
  • STND_MINUS carries global PACK_MINUS down from the top board to the bottom board through a brass standoff.
  • ROD1 is strictly dual-purpose: structural spine plus electrical conductor carrying N_C6_TOP from bottom board to the top board.
Locked Footprint and Geometry Constraints
  • Bottom-board capacitor placements are hard constraints:
    • C1 at (0, -10)
    • C4 at (16.887, -9.75)
    • C2 at (8.66, 5)
    • C5 at (0, 19.5)
    • C3 at (-8.66, 5)
    • C6 at (-16.887, -9.75)
  • Bottom-board resistor placements are hard constraints:
    • R1 at (0, 11), rotation 180 deg
    • R4 at (24.249, -14), rotation -60 deg
    • R2 at (9.526, -5.5), rotation -60 deg
    • R5 at (0, 28), rotation 180 deg
    • R3 at (-9.526, -5.5), rotation -120 deg
    • R6 at (-24.249, -14), rotation -120 deg
  • Bottom-board interconnect placements are hard constraints:
    • TERM1_FRONT at (0, -21)
    • TERM2_FRONT at (0, 35)
    • TERM3_FRONT at (31, 7)
    • TERM4_FRONT at (-31, 7)
    • STND_PLUS at (-12, -12)
    • STND_MINUS at (12, -12)
    • ROD1 at (0, 0)
  • Bottom-board terminal geometry is locked to KiCad v0.4:
    • TERM1_FRONT to TERM4_FRONT: 6 mm x 6 mm plated pad, 2.5 mm drill
    • STND_PLUS and STND_MINUS: 8 mm plated pad, 3.2 mm drill
    • ROD1: dual-feature central rod with 3.5 mm mechanical hole and 8 mm plated electrical pad tied to N_C6_TOP
Net Topology from the KiCad Bottom Board
  • PACK_PLUS feeds C1, R1, TERM1_FRONT, TERM2_FRONT, and STND_PLUS.
  • Intermediate chain nets are N_C1_C4, N_C4_C2, N_C2_C5, N_C5_C3, and N_C3_C6.
  • The lower-board output to the upper board is N_C6_TOP through ROD1.
  • PACK_MINUS is present on the lower board through TERM3_FRONT, TERM4_FRONT, and STND_MINUS.
Layout Intent
  • Maintain a 2-layer board stackup.
  • Use heavy copper zones for the high-current path.
  • Use solid/direct-connect copper for PACK_PLUS, PACK_MINUS, N_C1_C4, N_C4_C2, N_C2_C5, N_C5_C3, N_C3_C6, and N_C6_TOP.
  • Do not allow thermal spokes on any high-current pad or copper zone attachment.
  • Copy the KiCad trefoil geometry exactly except for minor DFM clearance massage that preserves the mating geometry and current-carrying intent.
Superseded Prior Assumptions
  • Eaton HV1625-2R7256-R is no longer the locked capacitor choice.
  • ALD active balancer ICs are no longer the locked balancing method.
  • Any earlier assumptions about ESC pads on the bottom board are superseded by the locked v0.4 charging-terminal and standoff architecture.
  • No-potting is the current locked assumption.

  • Locked Architecture

  • Locked Capacitor Specification

  • Bottom Board Topology

  • Bottom Board Mechanical Reference

  • Components and Interfaces

  • Locked Footprint and Geometry Constraints

  • Net Topology from the KiCad Bottom Board

  • Layout Intent

  • Superseded Prior Assumptions

Documents

Assets

Assets are files uploaded to this project which can be used in various ways.

600J Supercapacitor Power Module thumbnail
Production-grade 9-cell supercapacitor power module based on the locked KiCad architecture: Vishay 235 EDLC series stack with passive resistor balancing, a lower 6-cell custom bottom board plus upper board continuation, high-current copper zones, direct bus interfaces, and no potting.

Properties

Properties describe core aspects of the project.

Pricing & Availability

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