Smart Motor Starter PCB Design

flux

Yes — the best next sequence is:
  1. Swap in your corrected J1 part and reconnect only the real SIM pins
    • Connect only:
      • VCC -> SIM_VCC
      • RST -> SIM_RST
      • CLK -> SIM_CLK
      • I/O -> SIM_IO
      • GND and shell -> GND_CTRL
    • Leave VPP, RESERVED_1, and RESERVED_2 unconnected as true Not Connected pins. That is the correct fix path for NC-style pins, and Flux pin typing should reflect that in the part definition rather than by adding fake wires
  2. Re-run ERC immediately after the J1 replacement
    • If the part was created correctly, the false VPP power error should disappear.
    • Any remaining Missing Power errors after that are likely real and should be reviewed one by one.
    • For power-type pins, use the datasheet/part definition as the source of truth; don’t guess or force connections just to silence ERC
  3. Fix remaining real “Missing Power” items before touching layout
    • For each remaining power-input warning, decide whether the pin is:
      • a real supply pin that must be wired, or
      • an optional/NC pin that belongs in the part definition as Not Connected.
    • Likely candidates to review are unfinished support/status pins on U1, optional modem pins on U3, and any connector pins still typed incorrectly.
    • The rule is: wire real required pins, reclassify true NC pins, don’t fake-connect
  4. Triage floating pins into three buckets
    • Must connect: required control/power pins for the circuit to function.
    • Intentionally unused: optional pins on ESP1 and U3 that the datasheet allows to remain open.
    • Bad part-definition artifacts: pins that should really be Not Connected in the part itself.
    • This is exactly the recommended workflow for pin cleanup: use the datasheet as truth, map pins to the correct Flux pin types, and classify NC pins explicitly as Not Connected
  5. After ERC is down to only intentional opens, attack the airwires
    • The recommended PCB workflow is:
      • inspect
      • setup
      • annotate
      • group
      • ui-place
      • route
    • For your board, that means:
      • Re-pack parts to fit the 100 x 100 mm board
      • Place connectors, LEDs, SIM socket, relay, and mounting holes first
      • Maintain the AC/DC isolation boundary
      • Route power and relay current paths first
      • Then route low-speed control/UART/SIM signals
    • The layout guidance specifically says UI/mechanical parts and mounting features should be handled before final routing, and routing should prioritize net classes and current needs
  6. Use DRC/ERC as the stop condition
    • When J1 is corrected, the goal is:
      • no false connector power errors
      • only intentional floating optional pins
      • then reduce airwires to zero through placement/routing
    • After that, do the final BOM cleanup and export.
Practical order I’d follow
  1. Replace/reconnect corrected J1
  2. Re-run ERC
  3. Clear remaining real Missing Power items
  4. Clear/justify remaining floating pins on ESP1, U3, and U1
  5. Finish placement
  6. Route all airwires
  7. Re-run DRC/ERC
  8. Finalize BOM
If you want, I can turn this into a pin-by-pin cleanup checklist for J1, U3, ESP1, and U1.
Create cleanup checklist
Check remaining ERC
Inspect airwires
Review board layout
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Design Notes
Architecture Summary
  • Input power comes from a high-voltage isolated AC input supply block targeting 150 VAC to 300 VAC operation.
  • The isolated 5 V rail powers relay coils, external LED drivers, and battery charging.
  • An 18650 Li-ion cell is charged using TP4056 and protected using DW01A + FS8205A.
  • The protected battery rail feeds the SIM800L directly for high current bursts.
  • The ESP32-WROOM-32 is powered from the battery through a dedicated 3.3 V LDO with an isolation bead/filter from GSM burst noise.
  • Relay control uses PC817 + BC547 + flyback diode with GPIO26 and a 10k pulldown for boot-safe default OFF.
  • AC load switching includes an RC snubber 100 ohm + 100 nF X2 across the relay-switched AC path.
  • The layout will use a 2-layer stackup, separated high-voltage and SELV zones, minimum 5 mm isolation target from AC to low-voltage areas, and ESP32 antenna keepout.
Default Engineering Decisions
  • Use a rugged isolated 5 V AC-DC module for mains-derived power.
  • Use a low-Iq LDO for ESP32 instead of AMS1117 to reduce heat and dropout risk.
  • Power SIM800L from the protected battery rail with heavy local bulk capacitance.
  • Use star-ground intent by keeping noisy GSM return currents local and joining GSM and ESP32 grounds at one controlled point near the battery/protected ground entry.
  • Use transistor-driven external status LED outputs from 5 V for field-visible indicators.
Safety and Tutorial Notes to Preserve
  • Mark the AC section clearly with DANGER: HIGH VOLTAGE.
  • Segregate blocks as: AC Input, Charger and Battery Protection, ESP32 Control, GSM, Relay Isolation and Motor Output, External LED Outputs.
  • Add tutorial-grade comments and net labels for all key rails and interfaces.
  • Include assembly/silkscreen branding text: Designed by Krashi Technology.
Current Schematic Wiring Snapshot
  • AC input terminal feeds the isolated SMPS module directly on AC_LINE_IN and AC_NEUTRAL.
  • Added explicit protection parts: F1 mains fuse in series with line, RV1 MOV across line and neutral, and D3 TVS across 5V_ISO to GND_CTRL.
  • Added explicit protection parts and retained the final snubber implementation R18/C17; the earlier duplicate snubber placeholders R15/C14 were removed during cleanup.
  • Layout safety target is tightened to 6 mm minimum AC-to-SELV creepage/clearance, with a preferred routed isolation slot across the mains boundary.
  • Remaining electrical cleanup items: TP4056 TEMP handling, DW01A TD verification, SIM800L VBUS pin handling, SIM socket VPP handling, and cleanup of intentionally unused versus accidentally floating pins.
  • The isolated 5V_ISO rail powers the TP4056 charger, relay coil supply, and external LED driver collectors.
  • TP4056 battery output feeds VBAT_RAW.
  • DW01A plus FS8205A protect the battery path, while the current implemented battery rail feeding the modem and regulator is labeled VBAT_RAW in the schematic.
  • MCP1700 generates 3V3 for the ESP32 from the battery rail through FB1.
  • ESP32 GPIO0 has a pull-up and GPIO26 has a pull-down for safe relay boot behavior.
  • SIM800L is powered from VBAT_RAW and linked to the ESP32 over UART with a simple TX divider toward the modem RX input.
  • Relay drive uses optocoupler plus BC547 transistor and flyback diode.
  • Relay contacts route AC line from AC_LINE_IN to AC_LINE_SW and out to the field terminal.
  • SIM connector lines SIM_VCC, SIM_RST, SIM_CLK, and SIM_IO are protected by an ESD array.
  • J1 connector replacement plan: replace the current 2499165-1 symbol with a corrected part definition that marks C4 (Reserved), C6 (VPP), and C8 (Reserved) as Not Connected for standard SIM use. Keep the same footprint/pin order and reconnect only C1 VCC, C2 RST, C3 CLK, C5 GND, and C7 I/O. Do not tie VPP or Reserved pins to any rail just to suppress ERC.
  • Added a real SIM800L power-on control stage: ESP32 IO4 drives Q7 through R19, with R20 as base pulldown, and Q7 pulls PWRKEY low when firmware requests modem startup or shutdown.
  • Restored the three external LED outputs as transistor-driven 5 V channels using J3/J4/J5 screw terminals.

  • Architecture Summary

  • Default Engineering Decisions

  • Safety and Tutorial Notes to Preserve

  • Current Schematic Wiring Snapshot