The independent audit finished, but I cannot retrieve and reconcile its final report because no ACUs remain. That reconciliation, the full 12-item report, and final Stage 2 sign-off remain pending; no further project changes should be made until the audit is reviewed.
This project is the battery + Wi-Fi variant only. A separate PoE + Ethernet variant
exists but is NOT part of this board. Do not add Ethernet, PoE, RJ45, or magnetics
circuitry here.
Hard constraints — do not violate
Mechanical
ENC1 must be centred on the board outline. The assembly mounts to the faceplate
solely by the encoder's panel-mount nut, so the encoder shaft defines board position.
Place every other component relative to ENC1.
LED1 must be top-emitting — light exits perpendicular to the board. Never
side-emitting. LED1 must also be placed symmetrically with respect to ENC1: the knob
and the light are the two user-visible features, so the LED must read as deliberately
aligned to the encoder shaft, not incidentally positioned.
ENC1 = Bourns PEC11R-4220F-S0024 exactly: 24 detents AND 24 pulses per revolution.
Never substitute another PEC11R variant — several pair 12 pulses with 24 detents, which
makes firmware register only every other detent and cannot be fixed in software. This
part is through-hole and hand-soldered, so it does not need to exist in JLCPCB's
assembly library.
Power rails
3V3 from U3 buck-boost, always on.
LED_5V from U4 TPS60150 charge pump, switched by GPIO8, defaults OFF via a 100 kΩ
pull-down. Do not convert this to an always-on rail — the default-off behaviour through
reset, boot, and sleep is deliberate.
LED data must stay level-shifted through U5 (74AHCT1G125, or another TTL-threshold
"HCT" type). Never connect a 3.3 V GPIO directly to the LED data pin: the LED runs at
5 V and needs ~3.5 V for a valid logic high. A non-T "AHC" part will not work.
Branding
Add the "Vives" wordmark to the PCB silkscreen on the visible face. Keep it clear of pads,
fiducials, and the ESP32 antenna keepout. A vector master is required — the mark must stay
legible at silkscreen minimum line width.
Part selection policy
Every part must be orderable at JLCPCB. Prefer Basic Parts for passives — always
stocked, no per-part setup fee.
Before declaring a part unavailable, check sibling packaging suffixes. RGTT vs RGTR
and DRCT vs DRCR are the same silicon in cut-tape vs full-reel packaging. Three of four
"out of stock" parts on this board were resolved this way.
Bulk MLCCs and charge-pump capacitors must account for DC-bias derating — a nominal
22 µF part may deliver roughly half that at working voltage.
Deliberately out of scope for this board
Do not add these. They are recorded, deferred decisions — not oversights:
Magnetic 5 V charging input and its Schottky diode-OR
2×5 expansion connector
NTC / battery thermistor sensing. TS is intentionally bypassed (R8 10 kΩ to GND) per the
BQ24074 datasheet method; the design assumes a protected cell.
Approved addition, not yet built
Battery voltage sensing: 1 MΩ / 1 MΩ divider from BAT to a free ADC-capable GPIO.
No switching FET required — ~2 µA standing draw is acceptable.
GPIO map — do not reassign without flagging the conflict
Table
GPIO
Assignment
0
BOOT strap + SW1
4
ENC_SW
5
ENC_A
6
ENC_B
7
LED data (to U5)
8
RGB_EN
9
CHG_STATUS_N
10
PGOOD_N
19
USB D-
20
USB D+
Strapping pins GPIO3 / GPIO45 / GPIO46 must stay uncommitted.
U3 regulator — target configuration
TPS63802DLAT, LCSC C1849531, 10-pin VSON-HR HotRod, 3.0 × 2.0 mm, 0.5 mm pitch.
Adjustable output — there is no internal divider. Set 3.3 V with a 511 kΩ ±1% high-side
(3V3→FB) and 91 kΩ ±1% low-side (FB→GND); VFB = 500 mV nominal. These are TI's own
values for a 3.3 V output.
±1% tolerance is mandatory, not advisory: with 5% resistors the worst-case ratio gives
~3.63 V, which exceeds the ESP32-S3-WROOM-1's 3.6 V absolute maximum supply rating.
Never use 100 kΩ for the low-side resistor — the datasheet requires it to be less than
100 kΩ, and a ±1% 100 kΩ part measures up to 101 kΩ.
L3 = 0.47 µH nominal, saturation ≥ 5 A, DCR ≤ 30 mΩ, shielded, and inductance within
the validated 0.37–0.57 µH window across tolerance and current derating. The ≥ 5 A
saturation rating is mandatory: the IC's internal peak current limit is ~5 A, so a
lower-rated inductor would saturate before the IC current-limits.
The old L3 footprint (SMD_MAPI-4020) will almost certainly not match — verify, don't reuse.
Output capacitance: effective ≥ 7 µF after DC-bias derating (which can be −50%), with
22 µF nominal as the validated target. 10 µF nominal is explicitly an invalid combination
with a 0.47 µH inductor. Specify by effective capacitance, not nominal.
This part has no VINA pin — it needs no analog-supply RC filter.
This part has NO exposed thermal pad: 10 pads, 0.5 mm pitch, pad 8 enlarged, no centre
pad. The old TPS63001 had one on pin 11 — do not carry it over, and reject any generic
"VSON-10" footprint.
PG (pin 5) must be left unconnected with an explicit No-Connect flag, and must NOT be
named PGOOD/PGOOD_N or tied to the existing PGOOD_N net — that net already carries the
BQ24074's status to GPIO10. Do not add a pull-up to PG.
Scope
Hard constraints — do not violate
Mechanical
Power rails
Branding
Part selection policy
Deliberately out of scope for this board
Approved addition, not yet built
GPIO map — do not reassign without flagging the conflict