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Project Specification

Project

ESP32-C3 ADS1115 pH/ORP Sensor Interface

Current Design Scope

This project is a 3.3V-powered analog front-end for measuring pH, ORP, and temperature with an external ESP32-class controller. The board does not include batteries, TP4056 charging, debug headers, or an onboard ESP32. The ESP32 connection is through one 5-pin header carrying power and digital signals.

External Interface: J2

Use these names for firmware and wiring documentation:

Table

J2 Pin	Name	Direction	Purpose
1	3.3V	Input	External 3.3V supply from ESP32 board or regulated source
2	GND	Common	Common ground with ESP32 and probes
3	ADS1115 SDA	Bidirectional	I2C data to ADS1115 module
4	ADS1115 SCL	Input to ADS1115	I2C clock from ESP32
5	DS18B20 DQ	Bidirectional	1-Wire data for DS18B20 temperature probe

ADS1115 ADDR is fixed locally to GND through R14 = 10kΩ for default address 0x48. ADS1115 ALERT is intentionally unused/no-connect.

Power Architecture

External 3.3V enters at J2 pin 1 and feeds the filtered analog rail through R15.

Text
J2 pin 1 3.3V -> R15 10Ω -> FILTERED 3.3V
FILTERED 3.3V -> C17 10µF to GND
FILTERED 3.3V -> C18 100nF to GND

The FILTERED 3.3V rail powers U1 ADS1115 module, U2/U3 MCP6002 op-amps, J3 DS18B20 sensor power, pull-ups, and the analog bias/reference networks.

Sensor Architecture

J1 is the pH BNC input connector.
J5 is the ORP BNC input connector.
J3 is the DS18B20 temperature sensor header.
U1 ADS1115 module digitizes pH and ORP in differential mode.
U2 MCP6002 buffers the pH signal/reference paths.
U3 MCP6002 buffers the ORP signal/reference paths.

ADC Channel Map

Table

Measurement	ADS1115 Mode	Positive Input	Negative Input	Functional Net
pH	Differential	A0	A1	ADS1115 PH A0 - ADS1115 PH A1
ORP	Differential	A2	A3	ADS1115 ORP A2 - ADS1115 ORP A3

Firmware must read pH as A0-A1 and ORP as A2-A3. Do not use single-ended readings for the final measurement because the analog design relies on differential cancellation of the mid-supply reference.

Key Component Values

R15 = 10Ω analog supply filter resistor
C17 = 10µF analog rail bulk capacitor
C18 = 100nF analog rail bypass capacitor
R1/R2 = 100kΩ / 100kΩ mid-supply bias divider
C4 = 1µF bias filter
R3/R12 = 1MΩ pH/ORP probe input protection resistors
C7/C13 = 100pF high-impedance input RF filters
R5/R6/R9/R10 = 1kΩ ADS1115 input series filters/protection
C8/C14 = 100nF differential ADC input filters
C9/C10/C11/C12 = 100nF ADC input-to-GND filters
R11 = 4.7kΩ DS18B20 DQ pull-up
R14 = 10kΩ ADS1115 ADDR pull-down
R7/R8 = 10kΩ optional/DNP I2C pull-ups to FILTERED 3.3V. Leave unpopulated by default if the ADS1115 module already has onboard SDA/SCL pull-ups; populate only if no other I2C pull-ups are present.

Simulation Summary

Final simulation of the updated circuit with R15/C17/C18, local decoupling, and PH/ORP guard-ring modeling gives:

Table

Result	Value
Overall functional result	PASS
FILTERED 3.3V rail cutoff	~778 Hz
Rail attenuation at 100 Hz	-0.0716 dB
Rail attenuation at 1 kHz	-4.221 dB
Rail attenuation at 10 kHz	-22.18 dB
Rail attenuation at 100 kHz	-42.16 dB
pH/ORP differential bandwidth	~481.8 Hz
pH ADC range for ±414 mV probe input	A0 ≈ 1.236V to 2.064V, A1 ≈ 1.650V
ORP ADC range for ±1.0V probe input	A2 ≈ 0.650V to 2.650V, A3 ≈ 1.650V
Guard-ring verification	PH guard tied to PH REF; ORP guard tied to ORP REF; neither tied to GND

Simulation plots:

Final 3.3V rail filter response

pH and ORP differential gain vs frequency

pH transient step response

Firmware Requirements

Configure ADS1115 at address 0x48.
Treat R7/R8 as optional DNP hardware pull-ups: do not solder them if the ADS1115 module or ESP32 side already provides I2C pull-ups.
Use differential reads: A0-A1 for pH, A2-A3 for ORP.
Use lower ADS1115 data rates and averaging/median filtering for stable readings.
Read DS18B20 on J2 pin 5 / J3 pin 2 using 1-Wire.
Calibrate pH offset at pH 7 and slope using buffer solutions.
Temperature compensate pH slope using DS18B20 reading.

Current Validation Status

ERC reports no open errors or warnings. PCB routing is still expected to require DRC/airwire cleanup after layout routing.

Project
Current Design Scope
External Interface: J2
Power Architecture
Sensor Architecture
ADC Channel Map
Key Component Values
Simulation Summary
Firmware Requirements
Current Validation Status

Reviews