PCB Design for Smart Glasses

flux

Correct: for the PCB board outline, Flux needs a single closed outer contour. It generally won’t use an SVG icon with multiple paths/holes as the board shape directly.
For glasses, that means:
  • ✅ Use the SVG outer perimeter as the PCB outline.
  • ❌ Don’t expect the lens openings / holes inside the glasses icon to automatically become board cutouts.
  • ✅ Add lens openings separately as mechanical cutouts / routed slots if Flux supports them in your layout flow, or represent them later for fabrication.
  • ✅ Best SVG format: one flattened filled path for the outside edge, no groups, no strokes, no masks, no transforms.
So the workflow is usually:
  1. Export only the outside silhouette of the glasses frame as one closed path.
  2. Apply that as the PCB board outline.
  3. Add any internal holes/cutouts separately as mechanical features.
For now, if you want the front of a glasses frame as the PCB, make the board outline the solid glasses-front outer shape, then treat the lens openings as separate cutouts rather than part of the SVG board-shape path.
S

smonzon

ok I've fixed the SVG but why is it still not appearing?

flux

I’ll re-check the updated GlassesSVG asset flags and the active layout board-shape/asset rules to see what is still preventing it from showing.

flux

The fixed SVG was re-uploaded as a thumbnail/default asset again, so it still wasn’t eligible as a PCB board shape. I’ve now changed it to isPcbBoardShape=true, but the active board outline is still rectangle — the board shape does not automatically switch just because the asset exists.
Why it still may not appear:
  • The asset exists, but the PCB outline is still set to rectangle.
  • Flux’s board-shape rule needs the actual closed SVG path data, not just the asset name.
  • If you used an “asset” layout rule, that creates/controls a visual asset reference, not necessarily the manufactured PCB outline.
What to do next:
  1. Open the SVG file in a text editor.
  2. Copy the outer path’s d="M ... Z" value.
  3. Paste that path here.
  4. I’ll apply it directly as the board outline.
Apply outline and verify
Paste SVG path
Explain SVG path
Check current asset
Run layout review
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Files

Schematic

Layout

3D View

Schematic BOM and Net Notes
Scope
Schematic-only smart-glasses acoustic FMCW front-end. Board outline, placement, and routing are intentionally left to the user.
Implemented subsystem summary
Microphones
  • U1–U8: Knowles SPH0641LU4H-1 PDM MEMS microphones.
  • C1–C8: 100 nF 0402 ceramic local decoupling, one per microphone.
  • Power: VDD_MIC_1V8 and GND.
  • Clock: all microphones share PDM_CLK after R17 from connector-side PDM_CLK_SRC.
  • Data muxing:
    • PDM_DATA_A: U1 + U2
    • PDM_DATA_B: U3 + U4
    • PDM_DATA_C: U5 + U6
    • PDM_DATA_D: U7 + U8
  • SELECT mapping from SPH0641LU4H-1 datasheet:
    • SELECT = GND: asserts DATA on falling clock edge; FPGA latches on rising edge.
    • SELECT = VDD: asserts DATA on rising clock edge; FPGA latches on falling edge.
Transmit channels
  • U9: MCP4922T-E/SL left SPI DAC, channel A used.
  • U10: MCP4922T-E/SL right SPI DAC, channel A used.
  • U11: AD8397ARZ-REEL left wideband linear dual-op-amp driver.
  • U12: AD8397ARZ-REEL right wideband linear dual-op-amp driver.
  • LS1/LS2: SMS-1308MS-2-R library placeholders only; final part must be the user-selected broadband 4–8 ohm dynamic/voice-coil transducer.
  • Driver topology: DAC channel A feeds a BTL-style AD8397 stage. OUT1 follows DAC output; OUT2 is generated by unity inverting stage around shared VBIAS_TX; speaker is driven differentially through 1 ohm output isolation resistors.
  • Important caveat: MCP4922 is practical and simple but not an ideal high-fidelity 100 kHz arbitrary waveform DAC. If waveform quality becomes limiting, consider a faster waveform DAC/DDS such as AD9106-class hardware.
Connectors
Both connectors are 12-pin, 0.5 mm FFC/FPC Hirose FH12-12S-0.5SH(55).
Pin assignment for J1 and J2:

Table

PinJ1 LeftJ2 Right
1GNDGND
2VDD_MIC_1V8VDD_MIC_1V8
3PDM_CLK_SRCPDM_CLK_SRC
4GNDGND
5PDM_DATA_APDM_DATA_C
6PDM_DATA_BPDM_DATA_D
73V33V3
8SPI_L_SCKSPI_R_SCK
9GNDGND
10SPI_L_SDISPI_R_SDI
11SPI_L_CS_NSPI_R_CS_N
125V5V
ShieldGNDGND
BOM highlights
  • 8x Knowles SPH0641LU4H-1 PDM microphones.
  • 2x MCP4922T-E/SL dual SPI DACs; one channel used per side.
  • 2x AD8397ARZ-REEL wideband dual op amps; one IC per side.
  • 2x FH12-12S-0.5SH(55) 12-position 0.5 mm FFC/FPC connectors.
  • 2x dynamic speaker placeholders; replace with final broadband 4–8 ohm transducer.
  • 22x capacitors total currently: mic decoupling, DAC/amp decoupling, VBIAS bypass, and rail bulk.
  • 17x resistors total currently: SPI/PDM damping, output isolation, and bias/feedback network.
Timing / EMI sensitive nets
Prioritize these during placement/routing:
  1. PDM_CLK_SRC / PDM_CLK: common phase-coherent microphone clock; keep clean, short, and with solid return path.
  2. PDM_DATA_A–PDM_DATA_D: edge-timed PDM outputs; route with consistent return paths and avoid speaker-output coupling.
  3. SPI_L_SCK, SPI_R_SCK, SPI_L_SDI, SPI_R_SDI, SPI_L_CS_N, SPI_R_CS_N: fast ribbon/FFC digital lines; series resistors R1–R6 are 0 ohm placeholders for tuning.
  4. AD8397 output nets through R7–R10 to LS1/LS2: high-current analog outputs; keep loops compact and separated from mic data/clock.
  5. VBIAS_TX: quiet analog mid-bias reference for BTL driver inversion; keep away from speaker output current loops.
Open engineering risks
  • Final transducer is not selected. A normal 4–8 ohm dynamic speaker may have poor or unpredictable acoustic output near 100 kHz.
  • 5 V-only drive limits available ultrasonic acoustic power and current headroom.
  • MCP4922 settling rate is acceptable for early experiments but may limit high-quality FMCW waveform generation near the top of the target band.

  • Scope

  • Implemented subsystem summary

  • Microphones

  • Transmit channels

  • Connectors

  • BOM highlights

  • Timing / EMI sensitive nets

  • Open engineering risks