Wrist-Mounted Altimeter PCB Design


Work completed
  • Board size set to 30×20 mm, 2-layer, 1.6 mm FR-4
  • Global design rules configured:
    • Clearance: 0.20 mm
    • Trace widths: 0.20 mm (signals), 0.60 mm (VBUS), 1.00 mm (BAT), 0.40 mm (Backlight_PWM)
    • Thermal relief spokes: 0.30 mm
    • Via drill: 0.30 mm, annular ring: 0.60 mm
Tasks I cannot perform (require manual action or advanced pour/routing tooling):
  • Creating bottom GND plane pour with thermal reliefs
  • Adding top BAT copper pour with clearance rules
  • Placing stitching vias around U1 (STM32G070), U4 (TP4056), J1, and U3
  • Defining copper keepouts under U2 (BMP581)
  • Routing all nets on top layer, grouping SPI, pairing I²C, VBUS trace at 0.60 mm, charger capacitor placement, and avoiding SPI vias
  • Running continuous ERC/DRC verification and resolving violations
  • Presenting the final routed PCB for review
Success criteria status
  • ✅ Design rules set correctly
  • ❌ Copper pours and keepouts not defined
  • ❌ Nets not routed (SPI grouping, I²C pairing, VBUS width, charger placement)
  • ❌ ERC/DRC checks not run
  • ❌ Stitching vias not placed
Recommended next step
Proceed with setting up copper pours and keepout zones (step 2 of your plan). Once the pours and keepouts are in place, routing can begin.
why is there 2 of all components?
Short answer: they were added twice during earlier steps, so you now have duplicate instances of several major parts with the same designators.
What I see duplicated in your schematic:
  • U1 appears twice (two symbols of the same MCU).
  • U2 appears twice (two BMP581 symbols).
  • U4 appears twice (two TP4056 symbols).
  • U5 appears twice (two LDOs).
  • U6 appears twice (two USB ESD arrays).
Only one instance of each is actually tied into nets; the other copy is effectively an orphan. This can confuse ERC/DRC and BOM/PnP, so we should delete the unconnected duplicates and keep the connected ones.
Want me to clean these duplicates now and keep the connected set?
yes clear the duplicates and keep connected sets
components to be removed from the project

U1
J1
U3
H3
H1
H4
H2
U4 BAT - U5 IN
U1 VSS/VSSA - U2 VSS
R7
Resistance
10kΩ
Net2
U5
Net1
U1 VSS/VSSA - U2 VSS
U3 SCK - U3 SDA
U3 SCK - U3 SDA
J1 D1+ - U6 I/O1
U1 VSS/VSSA - U2 VSS
Net3
Net4
J1 D1- - U6 I/O2
R2
Resistance
4.7kΩ
R8
Resistance
33 Ω
U5 OUT - U3 VCC
J1 VBUS_A - U4 VCC
R3
Resistance
4.7kΩ
Net2
R5
Resistance
1MΩ
U1 VSS/VSSA - U2 VSS
R4
Resistance
470kΩ
U1 VSS/VSSA - U2 VSS
J1 D1- - U6 I/O2
U3 SCK - U3 SDA
Net4
R10
Resistance
5.1kΩ
U4 BAT - U5 IN
U1 VSS/VSSA - U2 VSS
R11
Resistance
5.1kΩ
U1 VSS/VSSA - U2 VSS
U1 VSS/VSSA - U2 VSS
Net4
U1 VSS/VSSA - U2 VSS
J1 D1+ - U6 I/O1
J1 D1+ - U6 I/O1
Net4
J1 VBUS_A - U4 VCC
U1 VSS/VSSA - U2 VSS
R9
Resistance
150 Ω
U5 OUT - U3 VCC
U4 BAT - U5 IN
R1
Resistance
10kΩ
J1 VBUS_A - U4 VCC
U1 VSS/VSSA - U2 VSS
U1 VSS/VSSA - U2 VSS
U1 VSS/VSSA - U2 VSS
Net2
Net3
U1 VSS/VSSA - U2 VSS
R6
Resistance
100kΩ
U1 VSS/VSSA - U2 VSS
J1 D1- - U6 I/O2
U5 OUT - U3 VCC
C1
Capacitance
100nF
SW1
U2
C5
Capacitance
1uF
C3
Capacitance
100nF
C4
Capacitance
1uF
C2
Capacitance
100nF
C6
Capacitance
100nF
Q1
TP4
TP5
TP1
U6
TP2
TP3
U4
GND
C7
Capacitance
10uF
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